diff options
| author | Andreas Färber <afaerber@suse.de> | 2015-12-15 01:20:57 +0100 |
|---|---|---|
| committer | Andreas Fritiofson <andreas.fritiofson@gmail.com> | 2015-12-29 20:38:05 +0000 |
| commit | a12f1cf34c26ff9f0c1c15ece0d1c6a2d8f3b394 (patch) | |
| tree | 27d3542ef66c64ad872e9bf832115ad2745dadf3 /tcl/target | |
| parent | fea90dd83fe7f0960d5af60e1453b4900cafabca (diff) | |
tcl/target: Add Renesas S7G2 config
Tested with Renesas DK-S7G2M v3.0 board.
Change-Id: Ia6acaf70271ed4eb7bc4e921552cbd2ff83f6acb
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3169
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'tcl/target')
| -rw-r--r-- | tcl/target/renesas_s7g2.cfg | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/tcl/target/renesas_s7g2.cfg b/tcl/target/renesas_s7g2.cfg new file mode 100644 index 00000000..a09377b2 --- /dev/null +++ b/tcl/target/renesas_s7g2.cfg @@ -0,0 +1,50 @@ +# +# Renesas Synergy S7 G2 w/ ARM Cortex-M4 @ 240 MHz +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME s7g2 +} + +if { [info exists CPU_JTAG_TAPID] } { + set _CPU_JTAG_TAPID $CPU_JTAG_TAPID +} else { + set _CPU_JTAG_TAPID 0x5ba00477 +} + +if { [info exists CPU_SWD_TAPID] } { + set _CPU_SWD_TAPID $CPU_SWD_TAPID +} else { + set _CPU_SWD_TAPID 0x5ba02477 +} + +source [find target/swj-dp.tcl] + +if { [using_jtag] } { + set _CPU_TAPID $_CPU_JTAG_TAPID +} else { + set _CPU_TAPID $_CPU_SWD_TAPID +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + # 640 KB On-Chip SRAM + set _WORKAREASIZE 0xa0000 +} + +$_TARGETNAME configure -work-area-phys 0x1ffe0000 \ + -work-area-size $_WORKAREASIZE -work-area-backup 0 + +if { ![using_hla] } { + cortex_m reset_config sysresetreq +} + +adapter_khz 1000 |