diff options
| author | Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> | 2015-04-09 18:01:35 +0200 |
|---|---|---|
| committer | Freddie Chopin <freddie.chopin@gmail.com> | 2015-11-12 20:20:33 +0000 |
| commit | 6b32fe4124ddcd5afc5612013c0e14c53842e750 (patch) | |
| tree | 3caf2dc6cd6cab29526856ba2ced75d647700ffa /tcl/target | |
| parent | d8ac9d5ac559aa6aaf6ef8cf6f704c6e6b75da3a (diff) | |
tcl: Add default hooks for STM32F0x
Keep clocks running in low power modes. Stop watchdogs from interfering
with the debug session. Set up PLL and increase clock at reset init.
Change-Id: I232d769d893d54e4ea9411c46c56b19587b69919
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-on: http://openocd.zylin.com/2707
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Diffstat (limited to 'tcl/target')
| -rw-r--r-- | tcl/target/stm32f0x.cfg | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/tcl/target/stm32f0x.cfg b/tcl/target/stm32f0x.cfg index ff6d7f14..2b48cfce 100644 --- a/tcl/target/stm32f0x.cfg +++ b/tcl/target/stm32f0x.cfg @@ -4,6 +4,7 @@ # stm32 devices support SWD transports only. # source [find target/swj-dp.tcl] +source [find mem_helper.tcl] if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME @@ -53,3 +54,33 @@ if {![using_hla]} { # perform a soft reset cortex_m reset_config sysresetreq } + +proc stm32f0x_default_reset_start {} { + # Reset clock is HSI (8 MHz) + adapter_khz 1000 +} + +proc stm32f0x_default_examine_end {} { + # Enable debug during low power modes (uses more power) + mmw 0x40015804 0x00000006 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP + + # Stop watchdog counters during halt + mmw 0x40015808 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP +} + +proc stm32f0x_default_reset_init {} { + # Configure PLL to boost clock to HSI x 6 (48 MHz) + mww 0x40021004 0x00100000 ;# RCC_CFGR = PLLMUL[2] + mmw 0x40021000 0x01000000 0 ;# RCC_CR[31:16] |= PLLON + mww 0x40022000 0x00000011 ;# FLASH_ACR = PRFTBE | LATENCY[0] + sleep 10 ;# Wait for PLL to lock + mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1] + + # Boost JTAG frequency + adapter_khz 8000 +} + +# Default hooks +$_TARGETNAME configure -event examine-end { stm32f0x_default_examine_end } +$_TARGETNAME configure -event reset-start { stm32f0x_default_reset_start } +$_TARGETNAME configure -event reset-init { stm32f0x_default_reset_init } |