aboutsummaryrefslogtreecommitdiff
path: root/tcl/target/stm32f2x.cfg
diff options
context:
space:
mode:
authorSpencer Oliver <ntfreak@users.sourceforge.net>2011-07-28 11:45:09 +0100
committerSpencer Oliver <ntfreak@users.sourceforge.net>2011-07-28 11:45:09 +0100
commit89f593d8cbd74eb1db5d6beb2e60e9844504db6e (patch)
treebe27e572157f75ee6bf8361bebabf9e393ddf7a9 /tcl/target/stm32f2x.cfg
parentc73342fbe77b0d0432ce189566e0e8383f2b7493 (diff)
cfg: update scripts to use new stm32 driver names
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
Diffstat (limited to 'tcl/target/stm32f2x.cfg')
-rw-r--r--tcl/target/stm32f2x.cfg61
1 files changed, 61 insertions, 0 deletions
diff --git a/tcl/target/stm32f2x.cfg b/tcl/target/stm32f2x.cfg
new file mode 100644
index 00000000..b8de3843
--- /dev/null
+++ b/tcl/target/stm32f2x.cfg
@@ -0,0 +1,61 @@
+# script for stm32f2xxx
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME stm32f2xxx
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0x10000
+}
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+#
+# Since we may be running of an RC oscilator, we crank down the speed a
+# bit more to be on the safe side. Perhaps superstition, but if are
+# running off a crystal, we can run closer to the limit. Note
+# that there can be a pretty wide band where things are more or less stable.
+jtag_khz 1000
+
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+#jtag scan chain
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # See STM Document RM0033
+ # Section 32.6.3 - corresponds to Cortex-M3 r2p0
+ set _CPUTAPID 0x4ba00477
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID ] } {
+ set _BSTAPID $BSTAPID
+} else {
+ # See STM Document RM0033
+ # Section 32.6.2
+ #
+ set _BSTAPID 0x06411041
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
+