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authorSpencer Oliver <spen@spen-soft.co.uk>2012-08-23 21:03:29 +0100
committerFreddie Chopin <freddie.chopin@gmail.com>2012-08-29 06:24:36 +0000
commit2ce4e31bbcfabc06b7ac71d2e507e707d293c5c0 (patch)
tree2b6686f334bcb1d0123fa204938d6a419a7348de /tcl/target/lpc4350.cfg
parent4be685c6167e8ac340cd383f0a0a61faaa45f3f8 (diff)
cfg: update for target's that support cortex_m AIRCR SYSRESETREQ
If the target supports SYSRESETREQ make sure we use that as the default if srst is not fitted/configured. Change-Id: I24c907493134506320e69c1218702930629c1cdc Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/792 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Diffstat (limited to 'tcl/target/lpc4350.cfg')
-rw-r--r--tcl/target/lpc4350.cfg4
1 files changed, 4 insertions, 0 deletions
diff --git a/tcl/target/lpc4350.cfg b/tcl/target/lpc4350.cfg
index 63d13079..6614383b 100644
--- a/tcl/target/lpc4350.cfg
+++ b/tcl/target/lpc4350.cfg
@@ -42,3 +42,7 @@ jtag newtap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \
target create $_CHIPNAME.m4 cortex_m3 -chain-position $_CHIPNAME.m4
target create $_CHIPNAME.m0 cortex_m3 -chain-position $_CHIPNAME.m0
+
+# if srst is not fitted use SYSRESETREQ to
+# perform a soft reset
+cortex_m3 reset_config sysresetreq