diff options
| author | Andreas Färber <afaerber@suse.de> | 2016-05-14 20:21:49 +0200 |
|---|---|---|
| committer | Freddie Chopin <freddie.chopin@gmail.com> | 2016-05-20 21:38:03 +0100 |
| commit | 0c8ec7c826c60391034fe5f0ea90f8538ac94b38 (patch) | |
| tree | 3f1bf74454812f49bf5f2994a6eddc41677c99d8 /tcl/target/lpc1xxx.cfg | |
| parent | f630fac2e72af502d12139fdc864a01a4da7c868 (diff) | |
Fix spelling of ARM Cortex
It's Cortex-Xn, not Cortex Xn or cortex xn or cortex-xn or CORTEX-Xn
or CortexXn. Further it's Cortex-M0+, not M0plus.
Cf. http://www.arm.com/products/processors/index.php
Consistently write it the official way, so that it stops propagating.
Originally spotted in the documentation, it mainly affects code comments
but also Atmel SAM3/SAM4/SAMV, NiietCM4 and SiM3x flash driver output.
Found via:
git grep -i "Cortex "
git grep -i "Cortex-" | grep -v "Cortex-" | grep -v ".cpu"
git grep -i "CortexM"
Change-Id: Ic7b6ca85253e027f6f0f751c628d1a2a391fe914
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3483
Tested-by: jenkins
Reviewed-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Diffstat (limited to 'tcl/target/lpc1xxx.cfg')
| -rw-r--r-- | tcl/target/lpc1xxx.cfg | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/tcl/target/lpc1xxx.cfg b/tcl/target/lpc1xxx.cfg index 226425d4..9c10e9f9 100644 --- a/tcl/target/lpc1xxx.cfg +++ b/tcl/target/lpc1xxx.cfg @@ -56,7 +56,7 @@ if { [info exists CPUTAPID] } { # Allow user override set _CPUTAPID $CPUTAPID } else { - # LPC8xx/LPC11xx/LPC12xx use a Cortex M0/M0+ core, LPC13xx/LPC17xx use a Cortex M3 core,LPC40xx use a Cortex-M4F core. + # LPC8xx/LPC11xx/LPC12xx use a Cortex-M0/M0+ core, LPC13xx/LPC17xx use a Cortex-M3 core, LPC40xx use a Cortex-M4F core. if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" } { set _CPUTAPID 0x0bb11477 } elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } { @@ -148,10 +148,10 @@ if {[using_jtag]} { jtag_ntrst_delay 200 } -# LPC8xx (Cortex M0+ core) support SYSRESETREQ -# LPC11xx/LPC12xx (Cortex M0 core) support SYSRESETREQ -# LPC13xx/LPC17xx (Cortex M3 core) support SYSRESETREQ -# LPC40xx (Cortex M4F core) support SYSRESETREQ +# LPC8xx (Cortex-M0+ core) support SYSRESETREQ +# LPC11xx/LPC12xx (Cortex-M0 core) support SYSRESETREQ +# LPC13xx/LPC17xx (Cortex-M3 core) support SYSRESETREQ +# LPC40xx (Cortex-M4F core) support SYSRESETREQ if {![using_hla]} { # if srst is not fitted use SYSRESETREQ to # perform a soft reset |