diff options
author | Vandra Akos <axos88@gmail.com> | 2012-05-27 12:50:04 +0200 |
---|---|---|
committer | Freddie Chopin <freddie.chopin@gmail.com> | 2012-08-01 21:15:01 +0000 |
commit | ee8df96b2b064fd666e9a3aa8b8f03eb0f2bd75f (patch) | |
tree | 1950c717d51996de6258fe2b5aa5b52317e05c3a /tcl/target/lpc1756.cfg | |
parent | 8fe2bed92c993242038c60273d1bb73f572e795e (diff) |
added target configs for the lpc17xx devices
lpc1751, lpc1752, lpc1754, lpc1756, lpc1758, lpc1759
lpc1763, lpc1764, lpc1765, lpc1766, lpc1767, lpc1768, lpc1769
Change-Id: I740b66930cd379c9390f3c1031cdbada747a6ce4
Signed-off-by: Vandra Akos <axos88@gmail.com>
Reviewed-on: http://openocd.zylin.com/676
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Tested-by: jenkins
Diffstat (limited to 'tcl/target/lpc1756.cfg')
-rw-r--r-- | tcl/target/lpc1756.cfg | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/tcl/target/lpc1756.cfg b/tcl/target/lpc1756.cfg new file mode 100644 index 00000000..8110727f --- /dev/null +++ b/tcl/target/lpc1756.cfg @@ -0,0 +1,21 @@ +# !!!!!!!!!!!! +# ! UNTESTED ! +# !!!!!!!!!!!! + +# NXP LPC1756 Cortex-M3 with 256kB Flash and 16kB+16kB Local On-Chip SRAM, +set CHIPNAME lpc1756 +set CPUTAPID 0x4ba00477 +set CPURAMSIZE 0x8000 +set CPUROMSIZE 0x40000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 4000 + +#Include the main configuration file. +source [find target/lpc17xx.cfg]; |