diff options
| author | Paul Fertser <fercerpav@gmail.com> | 2013-10-13 19:15:24 +0400 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2013-10-29 22:49:35 +0000 |
| commit | d4e195ad1b544b0396cab4c70437371958769196 (patch) | |
| tree | 610413e0cdd6d95d282b950e571913eeec5a7c4e /tcl/target/at91sam9260_ext_RAM_ext_flash.cfg | |
| parent | 2b10052097c882cf0ed92748c15ff6ee001c1f8f (diff) | |
Remove jtag_rclk from target configs
Some boards might have RCLK omitted from the JTAG connector and if the
interface claims support for it, OpenOCD will end up trying to use
RCLK while it's actually impossible.
This is a "cd tcl/target; sed -i s/jtag_rclk/adapter_khz/g *" patch.
Change-Id: Iee7337107bc1457966b104389ba9db75a9c860b4
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1695
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Mathias Küster <kesmtp@freenet.de>
Diffstat (limited to 'tcl/target/at91sam9260_ext_RAM_ext_flash.cfg')
| -rw-r--r-- | tcl/target/at91sam9260_ext_RAM_ext_flash.cfg | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg index f7121ec9..9ab74090 100644 --- a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg +++ b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg @@ -6,7 +6,7 @@ source [find target/at91sam9261.cfg] reset_config trst_and_srst -jtag_rclk 4 +adapter_khz 4 adapter_nsrst_delay 200 jtag_ntrst_delay 200 @@ -14,7 +14,7 @@ jtag_ntrst_delay 200 scan_chain $_TARGETNAME configure -event reset-start { # at reset chip runs at 32khz - jtag_rclk 8 + adapter_khz 8 } $_TARGETNAME configure -event reset-init {at91sam_init} @@ -46,7 +46,7 @@ proc at91sam_init { } { sleep 10 ;# wait 10 ms # Now run at anything fast... ie: 10mhz! - jtag_rclk 10000 ;# Increase JTAG Speed to 6 MHz + adapter_khz 10000 ;# Increase JTAG Speed to 6 MHz mww 0xffffec00 0x0a0a0a0a ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit mww 0xffffec04 0x0b0b0b0b ;# SMC_PULSE0 |