diff options
author | Antonio Borneo <borneo.antonio@gmail.com> | 2010-12-19 01:22:53 +0800 |
---|---|---|
committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2010-12-18 21:04:22 +0100 |
commit | 30da7c67cec8b315972377b5389735ff11f6042c (patch) | |
tree | f5735bd53edf0b43ef27c5058fdab817d2034462 /tcl/board/mini2440.cfg | |
parent | af3f77a1777e4f28ec1a14122f4800ca3467e4c7 (diff) |
TCL: fix non TCL comments
End of line comments fixed with ';' before '#'.
Added few additional 'space' to keep indentation in
multi-line comments.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'tcl/board/mini2440.cfg')
-rw-r--r-- | tcl/board/mini2440.cfg | 60 |
1 files changed, 30 insertions, 30 deletions
diff --git a/tcl/board/mini2440.cfg b/tcl/board/mini2440.cfg index 16889654..c5adac36 100644 --- a/tcl/board/mini2440.cfg +++ b/tcl/board/mini2440.cfg @@ -182,10 +182,10 @@ proc init_2440 { } { # usb clock are off 12mHz xtal #----------------------------------------------- - mww phys 0x4C000014 0x00000005 # Clock Divider control Reg - mww phys 0x4C000000 0xFFFFFFFF # LOCKTIME count register - mww phys 0x4C000008 0x00038022 # UPPLCON USB clock config Reg - mww phys 0x4C000004 0x0007F021 # MPPLCON Proc clock config Reg + mww phys 0x4C000014 0x00000005 ;# Clock Divider control Reg + mww phys 0x4C000000 0xFFFFFFFF ;# LOCKTIME count register + mww phys 0x4C000008 0x00038022 ;# UPPLCON USB clock config Reg + mww phys 0x4C000004 0x0007F021 ;# MPPLCON Proc clock config Reg #----------------------------------------------- # Configure Memory controller @@ -193,45 +193,45 @@ proc init_2440 { } { # DRAM - 64MB - 32 bit bus, uses BANKCON6 BANKCON7 #----------------------------------------------- - mww phys 0x48000000 0x22111112 # BWSCON - Bank and Bus Width - mww phys 0x48000010 0x00001112 # BANKCON4 - ? - mww phys 0x4800001c 0x00018009 # BANKCON6 - DRAM - mww phys 0x48000020 0x00018009 # BANKCON7 - DRAM - mww phys 0x48000024 0x008E04EB # REFRESH - DRAM - mww phys 0x48000028 0x000000B2 # BANKSIZE - DRAM - mww phys 0x4800002C 0x00000030 # MRSRB6 - DRAM - mww phys 0x48000030 0x00000030 # MRSRB7 - DRAM + mww phys 0x48000000 0x22111112 ;# BWSCON - Bank and Bus Width + mww phys 0x48000010 0x00001112 ;# BANKCON4 - ? + mww phys 0x4800001c 0x00018009 ;# BANKCON6 - DRAM + mww phys 0x48000020 0x00018009 ;# BANKCON7 - DRAM + mww phys 0x48000024 0x008E04EB ;# REFRESH - DRAM + mww phys 0x48000028 0x000000B2 ;# BANKSIZE - DRAM + mww phys 0x4800002C 0x00000030 ;# MRSRB6 - DRAM + mww phys 0x48000030 0x00000030 ;# MRSRB7 - DRAM #----------------------------------------------- # Now port configuration for enables for memory # and other stuff. #----------------------------------------------- - mww phys 0x56000000 0x007FFFFF # GPACON + mww phys 0x56000000 0x007FFFFF ;# GPACON - mww phys 0x56000010 0x00295559 # GPBCON - mww phys 0x56000018 0x000003FF # GPBUP (PULLUP ENABLE) - mww phys 0x56000014 0x000007C2 # GPBDAT + mww phys 0x56000010 0x00295559 ;# GPBCON + mww phys 0x56000018 0x000003FF ;# GPBUP (PULLUP ENABLE) + mww phys 0x56000014 0x000007C2 ;# GPBDAT - mww phys 0x56000020 0xAAAAA6AA # GPCCON - mww phys 0x56000028 0x0000FFFF # GPCUP - mww phys 0x56000024 0x00000020 # GPCDAT + mww phys 0x56000020 0xAAAAA6AA ;# GPCCON + mww phys 0x56000028 0x0000FFFF ;# GPCUP + mww phys 0x56000024 0x00000020 ;# GPCDAT - mww phys 0x56000030 0xAAAAAAAA # GPDCON - mww phys 0x56000038 0x0000FFFF # GPDUP + mww phys 0x56000030 0xAAAAAAAA ;# GPDCON + mww phys 0x56000038 0x0000FFFF ;# GPDUP - mww phys 0x56000040 0xAAAAAAAA # GPECON - mww phys 0x56000048 0x0000FFFF # GPEUP + mww phys 0x56000040 0xAAAAAAAA ;# GPECON + mww phys 0x56000048 0x0000FFFF ;# GPEUP - mww phys 0x56000050 0x00001555 # GPFCON - mww phys 0x56000058 0x0000007F # GPFUP - mww phys 0x56000054 0x00000000 # GPFDAT + mww phys 0x56000050 0x00001555 ;# GPFCON + mww phys 0x56000058 0x0000007F ;# GPFUP + mww phys 0x56000054 0x00000000 ;# GPFDAT - mww phys 0x56000060 0x00150114 # GPGCON - mww phys 0x56000068 0x0000007F # GPGUP + mww phys 0x56000060 0x00150114 ;# GPGCON + mww phys 0x56000068 0x0000007F ;# GPGUP - mww phys 0x56000070 0x0015AAAA # GPHCON - mww phys 0x56000078 0x000003FF # GPGUP + mww phys 0x56000070 0x0015AAAA ;# GPHCON + mww phys 0x56000078 0x000003FF ;# GPGUP } |