armv7m: remove gdb register hacks

Now that we support the target description format we do not need
these hacks anymore, we can now tell gdb what registers we support.

Change-Id: Ie774231d296420b35efcf708bc4435475c87ff5e
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1617
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>

4 files changed, 1 insertions, 82 deletions

diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index d32352a7..d7b54045 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -69,19 +69,6 @@ const int armv7m_msp_reg_map[17] = {
 	ARMV7M_xPSR,
 };
 
-#ifdef ARMV7_GDB_HACKS
-uint8_t armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
-
-struct reg armv7m_gdb_dummy_cpsr_reg = {
-	.name = "GDB dummy cpsr register",
-	.value = armv7m_gdb_dummy_cpsr_value,
-	.dirty = 0,
-	.valid = 1,
-	.size = 32,
-	.arch_info = NULL,
-};
-#endif
-
 /*
  * These registers are not memory-mapped.  The ARMv7-M profile includes
  * memory mapped registers too, such as for the NVIC (interrupt controller)
@@ -281,17 +268,7 @@ int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
 	for (i = 16; i < 24; i++)
 		(*reg_list)[i] = &arm_gdb_dummy_fp_reg;
 	(*reg_list)[24] = &arm_gdb_dummy_fps_reg;
-
-#ifdef ARMV7_GDB_HACKS
-	/* use dummy cpsr reg otherwise gdb may try and set the thumb bit */
-	(*reg_list)[25] = &armv7m_gdb_dummy_cpsr_reg;
-
-	/* ARMV7M is always in thumb mode, try to make GDB understand this
-	 * if it does not support this arch */
-	*((char *)armv7m->arm.pc->value) |= 1;
-#else
 	(*reg_list)[25] = &armv7m->arm.core_cache->reg_list[ARMV7M_xPSR];
-#endif
 
 	return ERROR_OK;
 }
@@ -552,10 +529,6 @@ struct reg_cache *armv7m_build_reg_cache(struct target *target)
 	struct arm_reg *arch_info = calloc(num_regs, sizeof(struct arm_reg));
 	int i;
 
-#ifdef ARMV7_GDB_HACKS
-	register_init_dummy(&armv7m_gdb_dummy_cpsr_reg);
-#endif
-
 	/* Build the process context cache */
 	cache->name = "arm v7m registers";
 	cache->next = NULL;
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index d028f4ef..92bada0a 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -30,16 +30,6 @@
 #include "arm_adi_v5.h"
 #include "arm.h"
 
-/* define for enabling armv7 gdb workarounds */
-#if 1
-#define ARMV7_GDB_HACKS
-#endif
-
-#ifdef ARMV7_GDB_HACKS
-extern uint8_t armv7m_gdb_dummy_cpsr_value[];
-extern struct reg armv7m_gdb_dummy_cpsr_reg;
-#endif
-
 extern const int armv7m_psp_reg_map[];
 extern const int armv7m_msp_reg_map[];
 
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index fbe635bd..5892a0e8 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -433,17 +433,6 @@ static int cortex_m3_debug_entry(struct target *target)
 	r = arm->cpsr;
 	xPSR = buf_get_u32(r->value, 0, 32);
 
-#ifdef ARMV7_GDB_HACKS
-	/* FIXME this breaks on scan chains with more than one Cortex-M3.
-	 * Instead, each CM3 should have its own dummy value...
-	 */
-	/* copy real xpsr reg for gdb, setting thumb bit */
-	buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
-	buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
-	armv7m_gdb_dummy_cpsr_reg.valid = r->valid;
-	armv7m_gdb_dummy_cpsr_reg.dirty = r->dirty;
-#endif
-
 	/* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
 	if (xPSR & 0xf00) {
 		r->dirty = r->valid;
@@ -1232,17 +1221,8 @@ int cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoin
 {
 	struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 
-	if (cortex_m3->auto_bp_type) {
+	if (cortex_m3->auto_bp_type)
 		breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
-#ifdef ARMV7_GDB_HACKS
-		if (breakpoint->length != 2) {
-			/* XXX Hack: Replace all breakpoints with length != 2 with
-			 * a hardware breakpoint. */
-			breakpoint->type = BKPT_HARD;
-			breakpoint->length = 2;
-		}
-#endif
-	}
 
 	if (breakpoint->type != BKPT_TYPE_BY_ADDR(breakpoint->address)) {
 		if (breakpoint->type == BKPT_HARD) {
@@ -1540,18 +1520,6 @@ static int cortex_m3_store_core_reg_u32(struct target *target,
 	struct armv7m_common *armv7m = target_to_armv7m(target);
 	struct adiv5_dap *swjdp = armv7m->arm.dap;
 
-#ifdef ARMV7_GDB_HACKS
-	/* If the LR register is being modified, make sure it will put us
-	 * in "thumb" mode, or an INVSTATE exception will occur. This is a
-	 * hack to deal with the fact that gdb will sometimes "forge"
-	 * return addresses, and doesn't set the LSB correctly (i.e., when
-	 * printing expressions containing function calls, it sets LR = 0.)
-	 * Valid exception return codes have bit 0 set too.
-	 */
-	if (num == ARMV7M_R14)
-		value |= 0x01;
-#endif
-
 	/* NOTE:  we "know" here that the register identifiers used
 	 * in the v7m header match the Cortex-M3 Debug Core Register
 	 * Selector values for R0..R15, xPSR, MSP, and PSP.
diff --git a/src/target/hla_target.c b/src/target/hla_target.c
index 078ac647..2db04f81 100644
--- a/src/target/hla_target.c
+++ b/src/target/hla_target.c
@@ -157,18 +157,6 @@ static int adapter_store_core_reg_u32(struct target *target,
 
 	LOG_DEBUG("%s", __func__);
 
-#ifdef ARMV7_GDB_HACKS
-	/* If the LR register is being modified, make sure it will put us
-	 * in "thumb" mode, or an INVSTATE exception will occur. This is a
-	 * hack to deal with the fact that gdb will sometimes "forge"
-	 * return addresses, and doesn't set the LSB correctly (i.e., when
-	 * printing expressions containing function calls, it sets LR = 0.)
-	 * Valid exception return codes have bit 0 set too.
-	 */
-	if (num == ARMV7M_R14)
-		value |= 0x01;
-#endif
-
 	/* NOTE:  we "know" here that the register identifiers used
 	 * in the v7m header match the Cortex-M3 Debug Core Register
 	 * Selector values for R0..R15, xPSR, MSP, and PSP.