diff options
| author | Spencer Oliver <spen@spen-soft.co.uk> | 2012-10-08 10:05:45 +0100 |
|---|---|---|
| committer | Freddie Chopin <freddie.chopin@gmail.com> | 2012-10-18 14:39:04 +0000 |
| commit | 7165e05cf64f5c24177239f9f9db577b45f1b52c (patch) | |
| tree | a8197b5d3b1ef19df06b4b97602ece36e06b2903 /src | |
| parent | 98a41bca6ed5711c972fdd75167ffc031377a456 (diff) | |
stlink: fix vector catch not being cleared
Seems after a reset the stlink is not clearing the vector catch (VC_CORERESET)
in the Debug Control Register.
This has the side effect if the user presses an external reset the core will
halt, this patch fixes that.
Change-Id: Ic3b2c3991b79cacbbd901c02b79613c2e204e71f
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/905
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/target/stm32_stlink.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/target/stm32_stlink.c b/src/target/stm32_stlink.c index aac1eecb..1c755084 100644 --- a/src/target/stm32_stlink.c +++ b/src/target/stm32_stlink.c @@ -325,6 +325,7 @@ static int stm32_stlink_load_context(struct target *target) static int stlink_debug_entry(struct target *target) { + struct stlink_interface_s *stlink_if = target_to_stlink(target); struct armv7m_common *armv7m = target_to_armv7m(target); struct arm *arm = &armv7m->arm; struct reg *r; @@ -337,6 +338,9 @@ static int stlink_debug_entry(struct target *target) stm32_stlink_load_context(target); + /* make sure we clear the vector catch bit */ + stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DEMCR, 0); + r = armv7m->core_cache->reg_list + ARMV7M_xPSR; xPSR = buf_get_u32(r->value, 0, 32); @@ -427,7 +431,12 @@ static int stm32_stlink_assert_reset(struct target *target) } stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DHCSR, DBGKEY|C_DEBUGEN); - stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DEMCR, VC_CORERESET); + + /* only set vector catch if halt is requested */ + if (target->reset_halt) + stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DEMCR, VC_CORERESET); + else + stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DEMCR, 0); if (jtag_reset_config & RESET_HAS_SRST) { if (!srst_asserted) { |