diff options
author | Spencer Oliver <spen@spen-soft.co.uk> | 2014-09-11 22:14:31 +0100 |
---|---|---|
committer | Spencer Oliver <spen@spen-soft.co.uk> | 2014-10-06 11:57:40 +0000 |
commit | 3160c66408af858c3064e54fb14f074e54ac6701 (patch) | |
tree | 26c57bb046e4c6157a524a31f7a41b4559c00fcc /src/target | |
parent | b675edcc95935cbdf77002db1e261536026f4cbe (diff) |
target: constify structures
Change-Id: I875cfab8dec4ade72ed9c9cd7d52baaca182a1ef
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/2295
Tested-by: jenkins
Diffstat (limited to 'src/target')
-rw-r--r-- | src/target/arm_adi_v5.c | 4 | ||||
-rw-r--r-- | src/target/arm_semihosting.c | 2 | ||||
-rw-r--r-- | src/target/armv7m.c | 4 | ||||
-rw-r--r-- | src/target/armv7m.h | 2 | ||||
-rw-r--r-- | src/target/avr32_ap7k.c | 4 | ||||
-rw-r--r-- | src/target/breakpoints.c | 8 | ||||
-rw-r--r-- | src/target/dsp563xx.c | 2 | ||||
-rw-r--r-- | src/target/dsp563xx_once.h | 6 | ||||
-rw-r--r-- | src/target/embeddedice.c | 6 | ||||
-rw-r--r-- | src/target/etb.c | 2 | ||||
-rw-r--r-- | src/target/etm.c | 2 | ||||
-rw-r--r-- | src/target/nds32_reg.c | 4 | ||||
-rw-r--r-- | src/target/openrisc/jsp_server.c | 2 | ||||
-rw-r--r-- | src/target/openrisc/or1k.c | 2 | ||||
-rw-r--r-- | src/target/openrisc/or1k_tap_vjtag.c | 2 | ||||
-rw-r--r-- | src/target/xscale.c | 2 |
16 files changed, 27 insertions, 27 deletions
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index 9f660702..a0595315 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -987,7 +987,7 @@ static int dap_rom_display(struct command_context *cmd_ctx, uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4; uint32_t component_base; unsigned part_num; - char *type, *full; + const char *type, *full; component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000); @@ -1046,7 +1046,7 @@ static int dap_rom_display(struct command_context *cmd_ctx, if (((c_cid1 >> 4) & 0x0f) == 9) { uint32_t devtype; unsigned minor; - char *major = "Reserved", *subtype = "Reserved"; + const char *major = "Reserved", *subtype = "Reserved"; retval = mem_ap_read_atomic_u32(dap, (component_base & 0xfffff000) | 0xfcc, diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c index 06a433f2..21b7809c 100644 --- a/src/target/arm_semihosting.c +++ b/src/target/arm_semihosting.c @@ -48,7 +48,7 @@ #include <helper/log.h> #include <sys/stat.h> -static int open_modeflags[12] = { +static const int open_modeflags[12] = { O_RDONLY, O_RDONLY | O_BINARY, O_RDWR, diff --git a/src/target/armv7m.c b/src/target/armv7m.c index 58cec588..99af3a87 100644 --- a/src/target/armv7m.c +++ b/src/target/armv7m.c @@ -44,7 +44,7 @@ #define _DEBUG_INSTRUCTION_EXECUTION_ #endif -static char *armv7m_exception_strings[] = { +static const char * const armv7m_exception_strings[] = { "", "Reset", "NMI", "HardFault", "MemManage", "BusFault", "UsageFault", "RESERVED", "RESERVED", "RESERVED", "RESERVED", "SVCall", @@ -148,7 +148,7 @@ int armv7m_restore_context(struct target *target) * They are assigned by vendors, which generally assign different numbers to * peripherals (such as UART0 or a USB peripheral controller). */ -char *armv7m_exception_string(int number) +const char *armv7m_exception_string(int number) { static char enamebuf[32]; diff --git a/src/target/armv7m.h b/src/target/armv7m.h index 575912fc..86c9aee2 100644 --- a/src/target/armv7m.h +++ b/src/target/armv7m.h @@ -33,7 +33,7 @@ extern const int armv7m_psp_reg_map[]; extern const int armv7m_msp_reg_map[]; -char *armv7m_exception_string(int number); +const char *armv7m_exception_string(int number); /* offsets into armv7m core register cache */ enum { diff --git a/src/target/avr32_ap7k.c b/src/target/avr32_ap7k.c index e1812ecc..55d1efb4 100644 --- a/src/target/avr32_ap7k.c +++ b/src/target/avr32_ap7k.c @@ -35,12 +35,12 @@ #include "avr32_regs.h" #include "avr32_ap7k.h" -static char *avr32_core_reg_list[] = { +static const char * const avr32_core_reg_list[] = { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", "sr" }; -static struct avr32_core_reg +static const struct avr32_core_reg avr32_core_reg_list_arch_info[AVR32NUMCOREREGS] = { {0, NULL, NULL}, {1, NULL, NULL}, diff --git a/src/target/breakpoints.c b/src/target/breakpoints.c index 5143afb7..b854f1f0 100644 --- a/src/target/breakpoints.c +++ b/src/target/breakpoints.c @@ -29,12 +29,12 @@ #include <helper/log.h> #include "breakpoints.h" -static char *breakpoint_type_strings[] = { +static const char * const breakpoint_type_strings[] = { "hardware", "software" }; -static char *watchpoint_rw_strings[] = { +static const char * const watchpoint_rw_strings[] = { "read", "write", "access" @@ -50,7 +50,7 @@ int breakpoint_add_internal(struct target *target, { struct breakpoint *breakpoint = target->breakpoints; struct breakpoint **breakpoint_p = &target->breakpoints; - char *reason; + const char *reason; int retval; int n; @@ -396,7 +396,7 @@ int watchpoint_add(struct target *target, uint32_t address, uint32_t length, struct watchpoint *watchpoint = target->watchpoints; struct watchpoint **watchpoint_p = &target->watchpoints; int retval; - char *reason; + const char *reason; while (watchpoint) { if (watchpoint->address == address) { diff --git a/src/target/dsp563xx.c b/src/target/dsp563xx.c index 2e7ac961..1cb18cf1 100644 --- a/src/target/dsp563xx.c +++ b/src/target/dsp563xx.c @@ -335,7 +335,7 @@ enum watchpoint_condition { ((s & 1) << 16) | ((w & 1) << 15) | ((d & 0x3f) << 8) | (p & 0x3f)) /* the gdb register list is send in this order */ -static uint8_t gdb_reg_list_idx[] = { +static const uint8_t gdb_reg_list_idx[] = { DSP563XX_REG_IDX_X1, DSP563XX_REG_IDX_X0, DSP563XX_REG_IDX_Y1, DSP563XX_REG_IDX_Y0, DSP563XX_REG_IDX_A2, DSP563XX_REG_IDX_A1, DSP563XX_REG_IDX_A0, DSP563XX_REG_IDX_B2, DSP563XX_REG_IDX_B1, DSP563XX_REG_IDX_B0, DSP563XX_REG_IDX_PC, DSP563XX_REG_IDX_SR, diff --git a/src/target/dsp563xx_once.h b/src/target/dsp563xx_once.h index b0be95bd..8835d553 100644 --- a/src/target/dsp563xx_once.h +++ b/src/target/dsp563xx_once.h @@ -63,9 +63,9 @@ #define DSP563XX_ONCE_NOREG 0x01F /* no register selected */ struct once_reg { - uint8_t num; - uint8_t addr; - uint8_t len; + const uint8_t num; + const uint8_t addr; + const uint8_t len; const char *name; uint32_t reg; }; diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c index 01688308..2d32c83a 100644 --- a/src/target/embeddedice.c +++ b/src/target/embeddedice.c @@ -54,9 +54,9 @@ static int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf); * From: ARM9E-S TRM, DDI 0165, table C-4 (and similar, for other cores) */ static const struct { - char *name; - unsigned short addr; - unsigned short width; + const char *name; + unsigned short addr; + unsigned short width; } eice_regs[] = { [EICE_DBG_CTRL] = { .name = "debug_ctrl", diff --git a/src/target/etb.c b/src/target/etb.c index 2ab35027..370c181a 100644 --- a/src/target/etb.c +++ b/src/target/etb.c @@ -27,7 +27,7 @@ #include "etb.h" #include "register.h" -static char *etb_reg_list[] = { +static const char * const etb_reg_list[] = { "ETB_identification", "ETB_ram_depth", "ETB_ram_width", diff --git a/src/target/etm.c b/src/target/etm.c index 17516e9c..0c27bc3d 100644 --- a/src/target/etm.c +++ b/src/target/etm.c @@ -67,7 +67,7 @@ struct etm_reg_info { uint8_t size; /* low-N of 32 bits */ uint8_t mode; /* RO, WO, RW */ uint8_t bcd_vers; /* 1.0, 2.0, etc */ - char *name; + const char *name; }; /* diff --git a/src/target/nds32_reg.c b/src/target/nds32_reg.c index 997f4ed3..f82ffbfc 100644 --- a/src/target/nds32_reg.c +++ b/src/target/nds32_reg.c @@ -26,7 +26,7 @@ static bool nds32_reg_init_done; static struct nds32_reg_s nds32_regs[TOTAL_REG_NUM]; -static struct nds32_reg_exception_s nds32_ex_reg_values[] = { +static const struct nds32_reg_exception_s nds32_ex_reg_values[] = { {IR0, 3, 0x3, 2}, {IR0, 3, 0x3, 3}, {IR1, 3, 0x3, 2}, @@ -358,7 +358,7 @@ const char *nds32_reg_symbolic_name(uint32_t number) bool nds32_reg_exception(uint32_t number, uint32_t value) { int i; - struct nds32_reg_exception_s *ex_reg_value; + const struct nds32_reg_exception_s *ex_reg_value; uint32_t field_value; i = 0; diff --git a/src/target/openrisc/jsp_server.c b/src/target/openrisc/jsp_server.c index 597bfcb6..83e03ae3 100644 --- a/src/target/openrisc/jsp_server.c +++ b/src/target/openrisc/jsp_server.c @@ -37,7 +37,7 @@ static char *jsp_port; * the client should be forced into character mode. However it doesn't make any difference. */ -static char *negotiate = +static const char * const negotiate = "\xFF\xFB\x03" /* IAC WILL Suppress Go Ahead */ "\xFF\xFB\x01" /* IAC WILL Echo */ "\xFF\xFD\x03" /* IAC DO Suppress Go Ahead */ diff --git a/src/target/openrisc/or1k.c b/src/target/openrisc/or1k.c index bd373a7f..aeef0a56 100644 --- a/src/target/openrisc/or1k.c +++ b/src/target/openrisc/or1k.c @@ -50,7 +50,7 @@ static int or1k_write_core_reg(struct target *target, int num); static struct or1k_core_reg *or1k_core_reg_list_arch_info; -struct or1k_core_reg_init or1k_init_reg_list[] = { +static const struct or1k_core_reg_init or1k_init_reg_list[] = { {"r0" , GROUP0 + 1024, "org.gnu.gdb.or1k.group0", NULL}, {"r1" , GROUP0 + 1025, "org.gnu.gdb.or1k.group0", NULL}, {"r2" , GROUP0 + 1026, "org.gnu.gdb.or1k.group0", NULL}, diff --git a/src/target/openrisc/or1k_tap_vjtag.c b/src/target/openrisc/or1k_tap_vjtag.c index 513d8a74..fcc832aa 100644 --- a/src/target/openrisc/or1k_tap_vjtag.c +++ b/src/target/openrisc/or1k_tap_vjtag.c @@ -61,7 +61,7 @@ #define OR1K_TAP_INST_IDCODE 0x2 #define OR1K_TAP_INST_DEBUG 0x8 -static char *id_to_string(unsigned char id) +static const char *id_to_string(unsigned char id) { switch (id) { case VJTAG_NODE_ID: diff --git a/src/target/xscale.c b/src/target/xscale.c index b64a1bff..8d97a89f 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -78,7 +78,7 @@ static const uint8_t xscale_debug_handler[] = { #include "xscale_debug.inc" }; -static char *const xscale_reg_list[] = { +static const char *const xscale_reg_list[] = { "XSCALE_MAINID", /* 0 */ "XSCALE_CACHETYPE", "XSCALE_CTRL", |