diff options
| author | Andreas Fritiofson <andreas.fritiofson@gmail.com> | 2011-10-25 00:47:21 +0200 |
|---|---|---|
| committer | Øyvind Harboe <oyvindharboe@gmail.com> | 2011-10-25 05:16:50 +0000 |
| commit | 8f76ca05d998ad8bcebb3d634a09386ea8c54e5e (patch) | |
| tree | c56d93212923f2048505842349f8126dc34a876b /src/target | |
| parent | f80ec2aa3723c59528198b275a348b6b8804929a (diff) | |
armv7a: fix scan-build warnings
"Value stored to 'retval' is never read": Check and propagate error
"Dereference of null pointer": Probably bogus, maybe triggered by the null
check on armv7a, so remove the check since it can't be null anyway.
Change-Id: I3bc44e52af1589ff40e6a42deda0ce7f3a25e397
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/119
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
Diffstat (limited to 'src/target')
| -rw-r--r-- | src/target/armv7a.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/target/armv7a.c b/src/target/armv7a.c index d74b99b2..67c563e6 100644 --- a/src/target/armv7a.c +++ b/src/target/armv7a.c @@ -147,6 +147,8 @@ int armv7a_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val) retval = dpm->instr_read_data_r0(dpm, ARMV4_5_MRC(15, 0, 0, 2, 0, ttb), &ttb); + if (retval != ERROR_OK) + return retval; retval = armv7a->armv7a_mmu.read_physical_memory(target, (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18), 4, 1, (uint8_t*)&first_lvl_descriptor); @@ -461,8 +463,6 @@ static int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t struct target *curr; struct armv7a_common *armv7a = target_to_armv7a(target); - if (armv7a == NULL) - LOG_ERROR("not an armv7a target"); l2x_cache = calloc(1, sizeof(struct armv7a_l2x_cache)); l2x_cache->base = base; l2x_cache->way = way; @@ -616,6 +616,7 @@ int armv7a_identify_cache(struct target *target) 2, 0, /* op1, op2 */ 0, 0, /* CRn, CRm */ &cache_selected); + if (retval!=ERROR_OK) goto done; /* select instruction cache*/ /* MCR p15, 2,<Rd>, c0, c0, 0; Write CSSELR */ /* [0] : 1 instruction cache selection , 0 data cache selection */ |