diff options
| author | Hsiangkai Wang <hsiangkai@gmail.com> | 2013-05-31 11:45:17 +0800 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2013-09-13 19:37:49 +0000 |
| commit | 586575c9dcc18154eeb4e893e554371c69ac0b9d (patch) | |
| tree | 641b5cd792865944762ccc75db51617b81e122a9 /src/target | |
| parent | 356f8a74122b45b383c141358ee7b11adf7a37f0 (diff) | |
nds32: modify nds commands implementation
Modify handle_nds32_memory_access_command: do not use DCache
setting to block user's setting.
Change-Id: I2d33f893773e2a2e3e2f26edde5938ef5902609d
Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1579
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'src/target')
| -rw-r--r-- | src/target/nds32_cmd.c | 40 |
1 files changed, 15 insertions, 25 deletions
diff --git a/src/target/nds32_cmd.c b/src/target/nds32_cmd.c index 3f243700..08923643 100644 --- a/src/target/nds32_cmd.c +++ b/src/target/nds32_cmd.c @@ -69,6 +69,7 @@ COMMAND_HANDLER(handle_nds32_memory_access_command) struct target *target = get_current_target(CMD_CTX); struct nds32 *nds32 = target_to_nds32(target); struct aice_port_s *aice = target_to_aice(target); + struct nds32_memory *memory = &(nds32->memory); if (!is_nds32(nds32)) { command_print(CMD_CTX, "current target isn't an Andes core"); @@ -76,33 +77,22 @@ COMMAND_HANDLER(handle_nds32_memory_access_command) } if (CMD_ARGC > 0) { - - /* If target has no cache, always use BUS mode - * to access memory. */ - struct nds32_memory *memory = &(nds32->memory); - - if (memory->dcache.line_size == 0) { - /* There is no Dcache. */ - nds32->memory.access_channel = NDS_MEMORY_ACC_BUS; - } else if (memory->dcache.enable == false) { - /* Dcache is disabled. */ - nds32->memory.access_channel = NDS_MEMORY_ACC_BUS; - } else { - /* There is Dcache and Dcache is enabled. */ - if (strcmp(CMD_ARGV[0], "bus") == 0) - nds32->memory.access_channel = NDS_MEMORY_ACC_BUS; - else if (strcmp(CMD_ARGV[0], "cpu") == 0) - nds32->memory.access_channel = NDS_MEMORY_ACC_CPU; - else /* default access channel is NDS_MEMORY_ACC_CPU */ - nds32->memory.access_channel = NDS_MEMORY_ACC_CPU; - } - - aice_memory_access(aice, nds32->memory.access_channel); + if (strcmp(CMD_ARGV[0], "bus") == 0) + memory->access_channel = NDS_MEMORY_ACC_BUS; + else if (strcmp(CMD_ARGV[0], "cpu") == 0) + memory->access_channel = NDS_MEMORY_ACC_CPU; + else /* default access channel is NDS_MEMORY_ACC_CPU */ + memory->access_channel = NDS_MEMORY_ACC_CPU; + + LOG_DEBUG("memory access channel is changed to %s", + NDS_MEMORY_ACCESS_NAME[memory->access_channel]); + + aice_memory_access(aice, memory->access_channel); + } else { + command_print(CMD_CTX, "memory access channel: %s", + NDS_MEMORY_ACCESS_NAME[memory->access_channel]); } - command_print(CMD_CTX, "memory access channel: %s", - NDS_MEMORY_ACCESS_NAME[nds32->memory.access_channel]); - return ERROR_OK; } |