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authorAlexander Kurz <akurz@blala.de>2016-02-26 21:54:22 +0100
committerAndreas Fritiofson <andreas.fritiofson@gmail.com>2016-02-29 19:14:06 +0000
commit34b32d613af913645bdb0b0e79f10bf0f302ff33 (patch)
tree75a902f72e2c942e2f23f710aecb5b0b4907a85f /src/target
parent6f05ec1e23a764b416fb8b6febcc4e439cd37e76 (diff)
arm_disassembler: bugfix, MRRC instruction not recognized
A copy-and-paste error in the arm_disassembler opcode evaluation disabled the recognition of MRRC instructions. According to the arm architecture ref. manual issue E or later, MRRC and MCRR instructions are identified by opcode bits 20-27: MCRR = 0xc4, MRRC = 0xc5. Error found by static code analysis using a semantic pattern to detect duplicated tests xand.cocci, see coccinellery.org Change-Id: Ic41426edb51c6816e11dc3d35ef9382ab34af486 Signed-off-by: Alexander Kurz <akurz@blala.de> Reviewed-on: http://openocd.zylin.com/3363 Reviewed-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Diffstat (limited to 'src/target')
-rw-r--r--src/target/arm_disassembler.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index 65086c2f..5cec6d67 100644
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -278,7 +278,7 @@ static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode,
uint8_t cp_num = (opcode & 0xf00) >> 8;
/* MCRR or MRRC */
- if (((opcode & 0x0ff00000) == 0x0c400000) || ((opcode & 0x0ff00000) == 0x0c400000)) {
+ if (((opcode & 0x0ff00000) == 0x0c400000) || ((opcode & 0x0ff00000) == 0x0c500000)) {
uint8_t cp_opcode, Rd, Rn, CRm;
char *mnemonic;