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authorPaul Fertser <fercerpav@gmail.com>2014-03-13 13:27:45 +0400
committerPaul Fertser <fercerpav@gmail.com>2015-03-09 06:39:28 +0000
commitca0e237d39a8e50c702cec4d825c4b44d63e4d4a (patch)
tree33ac92c86ee017dc27e8380237b0e1a3c96ce835 /src/target
parentd019080dfaa6c0c49228ecec2ad0c585ac65cb73 (diff)
arm11: initialise DPM and register cache before reading DSCR for the first time
When target was already halted during the initial examination, arm11_check_init() was trying to read, store and interpret DSCR contents before the DPM structure is initialised. This caused a segfault like described on http://sourceforge.net/apps/trac/openocd/ticket/65 . This is a totally untested attempt to fix this issue. Change-Id: I2fff115679a3f0023e7a88c749ccb5f045d6cf01 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2043 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'src/target')
-rw-r--r--src/target/arm11.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/target/arm11.c b/src/target/arm11.c
index 61f1f64e..0cb1d8c8 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -1177,6 +1177,12 @@ static int arm11_examine(struct target *target)
LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32,
device_id, implementor, didr);
+ /* Build register cache "late", after target_init(), since we
+ * want to know if this core supports Secure Monitor mode.
+ */
+ if (!target_was_examined(target))
+ CHECK_RETVAL(arm11_dpm_init(arm11, didr));
+
/* as a side-effect this reads DSCR and thus
* clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
* as suggested by the spec.
@@ -1186,12 +1192,6 @@ static int arm11_examine(struct target *target)
if (retval != ERROR_OK)
return retval;
- /* Build register cache "late", after target_init(), since we
- * want to know if this core supports Secure Monitor mode.
- */
- if (!target_was_examined(target))
- CHECK_RETVAL(arm11_dpm_init(arm11, didr));
-
/* ETM on ARM11 still uses original scanchain 6 access mode */
if (arm11->arm.etm && !target_was_examined(target)) {
*register_get_last_cache_p(&target->reg_cache) =