diff options
| author | Matthias Welwarsky <matthias.welwarsky@sysgo.com> | 2017-02-15 15:30:21 +0100 |
|---|---|---|
| committer | Paul Fertser <fercerpav@gmail.com> | 2017-02-24 09:17:22 +0000 |
| commit | d6535e0ce517bfb2c4c8acaef59eb73dd0c6d07c (patch) | |
| tree | cf86a58bca0a6698ae6ccd7a39a72ec1c7b9bb3d /src/target | |
| parent | 6fb9f2e3ee05d8ff6241e6d61f7de0e71afeb45c (diff) | |
aarch64: reset fixes
Make sure all core register caches are invalidated on reset
assert, make sure to re-init debug registers on deassert.
Change-Id: I82350d04cc3eaae5e35245d13d6c1fb0a8d59807
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3990
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Diffstat (limited to 'src/target')
| -rw-r--r-- | src/target/aarch64.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/src/target/aarch64.c b/src/target/aarch64.c index 65a5278e..d14b54dd 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -169,6 +169,13 @@ static int aarch64_init_debug_access(struct target *target) LOG_DEBUG(" "); + retval = mem_ap_write_atomic_u32(armv8->debug_ap, + armv8->debug_base + CPUV8_DBG_OSLAR, 0); + if (retval != ERROR_OK) { + LOG_DEBUG("Examine %s failed", "oslock"); + return retval; + } + /* Clear Sticky Power Down status Bit in PRSR to enable access to the registers in the Core Power Domain */ retval = mem_ap_read_atomic_u32(armv8->debug_ap, @@ -1256,8 +1263,10 @@ static int aarch64_assert_reset(struct target *target) } /* registers are now invalid */ - if (target_was_examined(target)) + if (target_was_examined(target)) { register_cache_invalidate(armv8->arm.core_cache); + register_cache_invalidate(armv8->arm.core_cache->next); + } target->state = TARGET_RESET; @@ -1290,7 +1299,7 @@ static int aarch64_deassert_reset(struct target *target) } } - return ERROR_OK; + return aarch64_init_debug_access(target); } static int aarch64_write_apb_ap_memory(struct target *target, |