Conform to C99 integer types format specifiers

Review and modify to conform to C99 integer types format specifiers.
Use arm-none-eabi toolchain to build successfully.

Change-Id: If855072a8f88886809309155ac6d031dcfcbc4b2
Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Signed-off-by: Hsiangkai <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1794
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>

3 files changed, 31 insertions, 31 deletions

diff --git a/src/target/openrisc/or1k.c b/src/target/openrisc/or1k.c
index 8d65d460..a7b3ed27 100644
--- a/src/target/openrisc/or1k.c
+++ b/src/target/openrisc/or1k.c
@@ -424,7 +424,7 @@ static int or1k_read_core_reg(struct target *target, int num)
 	if ((num >= 0) && (num < OR1KNUMCOREREGS)) {
 		reg_value = or1k->core_regs[num];
 		buf_set_u32(or1k->core_cache->reg_list[num].value, 0, 32, reg_value);
-		LOG_DEBUG("Read core reg %i value 0x%08x", num , reg_value);
+		LOG_DEBUG("Read core reg %i value 0x%08" PRIx32, num , reg_value);
 		or1k->core_cache->reg_list[num].valid = 1;
 		or1k->core_cache->reg_list[num].dirty = 0;
 	} else {
@@ -432,11 +432,11 @@ static int or1k_read_core_reg(struct target *target, int num)
 		int retval = du_core->or1k_jtag_read_cpu(&or1k->jtag,
 							 or1k->arch_info[num].spr_num, 1, &reg_value);
 		if (retval != ERROR_OK) {
-			LOG_ERROR("Error while reading spr 0x%08x", or1k->arch_info[num].spr_num);
+			LOG_ERROR("Error while reading spr 0x%08" PRIx32, or1k->arch_info[num].spr_num);
 			return retval;
 		}
 		buf_set_u32(or1k->core_cache->reg_list[num].value, 0, 32, reg_value);
-		LOG_DEBUG("Read spr reg %i value 0x%08x", num , reg_value);
+		LOG_DEBUG("Read spr reg %i value 0x%08" PRIx32, num , reg_value);
 	}
 
 	return ERROR_OK;
@@ -453,7 +453,7 @@ static int or1k_write_core_reg(struct target *target, int num)
 
 	uint32_t reg_value = buf_get_u32(or1k->core_cache->reg_list[num].value, 0, 32);
 	or1k->core_regs[num] = reg_value;
-	LOG_DEBUG("Write core reg %i value 0x%08x", num , reg_value);
+	LOG_DEBUG("Write core reg %i value 0x%08" PRIx32, num , reg_value);
 	or1k->core_cache->reg_list[num].valid = 1;
 	or1k->core_cache->reg_list[num].dirty = 0;
 
@@ -495,7 +495,7 @@ static int or1k_set_core_reg(struct reg *reg, uint8_t *buf)
 		int retval = du_core->or1k_jtag_write_cpu(&or1k->jtag,
 							  or1k_reg->spr_num, 1, &value);
 		if (retval != ERROR_OK) {
-			LOG_ERROR("Error while writing spr 0x%08x", or1k_reg->spr_num);
+			LOG_ERROR("Error while writing spr 0x%08" PRIx32, or1k_reg->spr_num);
 			return retval;
 		}
 	}
@@ -797,7 +797,7 @@ static int or1k_resume_or_step(struct target *target, int current,
 	uint32_t resume_pc;
 	uint32_t debug_reg_list[OR1K_DEBUG_REG_NUM];
 
-	LOG_DEBUG("Addr: 0x%x, stepping: %s, handle breakpoints %s\n",
+	LOG_DEBUG("Addr: 0x%" PRIx32 ", stepping: %s, handle breakpoints %s\n",
 		  address, step ? "yes" : "no", handle_breakpoints ? "yes" : "no");
 
 	if (target->state != TARGET_HALTED) {
@@ -862,7 +862,7 @@ static int or1k_resume_or_step(struct target *target, int current,
 		/* Single step past breakpoint at current address */
 		breakpoint = breakpoint_find(target, resume_pc);
 		if (breakpoint) {
-			LOG_DEBUG("Unset breakpoint at 0x%08x", breakpoint->address);
+			LOG_DEBUG("Unset breakpoint at 0x%08" PRIx32, breakpoint->address);
 			retval = or1k_remove_breakpoint(target, breakpoint);
 			if (retval != ERROR_OK)
 				return retval;
@@ -887,11 +887,11 @@ static int or1k_resume_or_step(struct target *target, int current,
 	if (!debug_execution) {
 		target->state = TARGET_RUNNING;
 		target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
-		LOG_DEBUG("Target resumed at 0x%08x", resume_pc);
+		LOG_DEBUG("Target resumed at 0x%08" PRIx32, resume_pc);
 	} else {
 		target->state = TARGET_DEBUG_RUNNING;
 		target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
-		LOG_DEBUG("Target debug resumed at 0x%08x", resume_pc);
+		LOG_DEBUG("Target debug resumed at 0x%08" PRIx32, resume_pc);
 	}
 
 	return ERROR_OK;
@@ -923,7 +923,7 @@ static int or1k_add_breakpoint(struct target *target,
 	struct or1k_du *du_core = or1k_to_du(or1k);
 	uint8_t data;
 
-	LOG_DEBUG("Adding breakpoint: addr 0x%08x, len %d, type %d, set: %d, id: %d",
+	LOG_DEBUG("Adding breakpoint: addr 0x%08" PRIx32 ", len %d, type %d, set: %d, id: %" PRId32,
 		  breakpoint->address, breakpoint->length, breakpoint->type,
 		  breakpoint->set, breakpoint->unique_id);
 
@@ -938,7 +938,7 @@ static int or1k_add_breakpoint(struct target *target,
 					 1,
 					 &data);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("Error while reading the instruction at 0x%08x",
+		LOG_ERROR("Error while reading the instruction at 0x%08" PRIx32,
 			   breakpoint->address);
 		return retval;
 	}
@@ -958,7 +958,7 @@ static int or1k_add_breakpoint(struct target *target,
 					  (uint8_t *)&or1k_trap_insn);
 
 	if (retval != ERROR_OK) {
-		LOG_ERROR("Error while writing OR1K_TRAP_INSTR at 0x%08x",
+		LOG_ERROR("Error while writing OR1K_TRAP_INSTR at 0x%08" PRIx32,
 			   breakpoint->address);
 		return retval;
 	}
@@ -980,7 +980,7 @@ static int or1k_remove_breakpoint(struct target *target,
 	struct or1k_common *or1k = target_to_or1k(target);
 	struct or1k_du *du_core = or1k_to_du(or1k);
 
-	LOG_DEBUG("Removing breakpoint: addr 0x%08x, len %d, type %d, set: %d, id: %d",
+	LOG_DEBUG("Removing breakpoint: addr 0x%08" PRIx32 ", len %d, type %d, set: %d, id: %" PRId32,
 		  breakpoint->address, breakpoint->length, breakpoint->type,
 		  breakpoint->set, breakpoint->unique_id);
 
@@ -996,7 +996,7 @@ static int or1k_remove_breakpoint(struct target *target,
 					  breakpoint->orig_instr);
 
 	if (retval != ERROR_OK) {
-		LOG_ERROR("Error while writing back the instruction at 0x%08x",
+		LOG_ERROR("Error while writing back the instruction at 0x%08" PRIx32,
 			   breakpoint->address);
 		return retval;
 	}
@@ -1032,7 +1032,7 @@ static int or1k_read_memory(struct target *target, uint32_t address,
 	struct or1k_common *or1k = target_to_or1k(target);
 	struct or1k_du *du_core = or1k_to_du(or1k);
 
-	LOG_DEBUG("Read memory at 0x%08x, size: %d, count: 0x%08x", address, size, count);
+	LOG_DEBUG("Read memory at 0x%08" PRIx32 ", size: %" PRIu32 ", count: 0x%08" PRIx32, address, size, count);
 
 	if (target->state != TARGET_HALTED) {
 		LOG_ERROR("Target not halted");
@@ -1090,7 +1090,7 @@ static int or1k_write_memory(struct target *target, uint32_t address,
 	struct or1k_common *or1k = target_to_or1k(target);
 	struct or1k_du *du_core = or1k_to_du(or1k);
 
-	LOG_DEBUG("Write memory at 0x%08x, size: %d, count: 0x%08x", address, size, count);
+	LOG_DEBUG("Write memory at 0x%08" PRIx32 ", size: %" PRIu32 ", count: 0x%08" PRIx32, address, size, count);
 
 	if (target->state != TARGET_HALTED) {
 		LOG_WARNING("Target not halted");
@@ -1377,7 +1377,7 @@ COMMAND_HANDLER(or1k_addreg_command_handler)
 
 	or1k_add_reg(target, &new_reg);
 
-	LOG_DEBUG("Add reg \"%s\" @ 0x%08x, group \"%s\", feature \"%s\"",
+	LOG_DEBUG("Add reg \"%s\" @ 0x%08" PRIx32 ", group \"%s\", feature \"%s\"",
 		  new_reg.name, addr, new_reg.group, new_reg.feature);
 
 	return ERROR_OK;
diff --git a/src/target/openrisc/or1k_du_adv.c b/src/target/openrisc/or1k_du_adv.c
index d0cc7f88..c3aceff1 100644
--- a/src/target/openrisc/or1k_du_adv.c
+++ b/src/target/openrisc/or1k_du_adv.c
@@ -283,7 +283,7 @@ static int adbg_ctrl_write(struct or1k_jtag *jtag_info, uint8_t regidx,
 	uint32_t opcode;
 	uint32_t opcode_len;
 
-	LOG_DEBUG("Write control register %d: 0x%08x", regidx, cmd_data[0]);
+	LOG_DEBUG("Write control register %" PRId8 ": 0x%08" PRIx32, regidx, cmd_data[0]);
 
 	int retval = adbg_select_ctrl_reg(jtag_info, regidx);
 	if (retval != ERROR_OK) {
@@ -419,7 +419,7 @@ static int adbg_wb_burst_read(struct or1k_jtag *jtag_info, int size,
 	int retval;
 	uint8_t opcode;
 
-	LOG_DEBUG("Doing burst read, word size %d, word count %d, start address 0x%08x",
+	LOG_DEBUG("Doing burst read, word size %d, word count %d, start address 0x%08" PRIx32,
 		  size, count, start_address);
 
 	/* Select the appropriate opcode */
@@ -508,7 +508,7 @@ retry_read_full:
 		crc_calc = adbg_compute_crc(crc_calc, data[i], 8);
 
 	if (crc_calc != crc_read) {
-		LOG_WARNING("CRC ERROR! Computed 0x%08x, read CRC 0x%08x", crc_calc, crc_read);
+		LOG_WARNING("CRC ERROR! Computed 0x%08" PRIx32 ", read CRC 0x%08" PRIx32, crc_calc, crc_read);
 		if (retry_full_crc++ < MAX_READ_CRC_RETRY)
 			goto retry_read_full;
 		else {
@@ -540,7 +540,7 @@ retry_read_full:
 				goto out;
 
 			addr = (err_data[0] >> 1) | (err_data[1] << 31);
-			LOG_WARNING("WB bus error during burst read, address 0x%08x, retrying!", addr);
+			LOG_WARNING("WB bus error during burst read, address 0x%08" PRIx32 ", retrying!", addr);
 
 			bus_error_retries++;
 			if (bus_error_retries > MAX_BUS_ERRORS) {
@@ -656,7 +656,7 @@ retry_full_write:
 		return retval;
 
 	if (!value) {
-		LOG_WARNING("CRC ERROR! match bit after write is %i (computed CRC 0x%08x)", value, crc_calc);
+		LOG_WARNING("CRC ERROR! match bit after write is %" PRIi8 " (computed CRC 0x%08" PRIx32 ")", value, crc_calc);
 		if (retry_full_crc++ < MAX_WRITE_CRC_RETRY)
 			goto retry_full_write;
 		else
@@ -684,7 +684,7 @@ retry_full_write:
 				return retval;
 
 			addr = (err_data[0] >> 1) | (err_data[1] << 31);
-			LOG_WARNING("WB bus error during burst write, address 0x%08x, retrying!", addr);
+			LOG_WARNING("WB bus error during burst write, address 0x%08" PRIx32 ", retrying!", addr);
 
 			bus_error_retries++;
 			if (bus_error_retries > MAX_BUS_ERRORS) {
@@ -831,7 +831,7 @@ static int or1k_adv_cpu_reset(struct or1k_jtag *jtag_info, int action)
 static int or1k_adv_jtag_read_memory(struct or1k_jtag *jtag_info,
 			    uint32_t addr, uint32_t size, int count, uint8_t *buffer)
 {
-	LOG_DEBUG("Reading WB%d at 0x%08x", size * 8, addr);
+	LOG_DEBUG("Reading WB%" PRId32 " at 0x%08" PRIx32, size * 8, addr);
 
 	int retval;
 	if (!jtag_info->or1k_jtag_inited) {
@@ -869,7 +869,7 @@ static int or1k_adv_jtag_read_memory(struct or1k_jtag *jtag_info,
 static int or1k_adv_jtag_write_memory(struct or1k_jtag *jtag_info,
 			     uint32_t addr, uint32_t size, int count, const uint8_t *buffer)
 {
-	LOG_DEBUG("Writing WB%d at 0x%08x", size * 8, addr);
+	LOG_DEBUG("Writing WB%" PRId32 " at 0x%08" PRIx32, size * 8, addr);
 
 	int retval;
 	if (!jtag_info->or1k_jtag_inited) {
diff --git a/src/target/openrisc/or1k_tap_vjtag.c b/src/target/openrisc/or1k_tap_vjtag.c
index 7d262720..513d8a74 100644
--- a/src/target/openrisc/or1k_tap_vjtag.c
+++ b/src/target/openrisc/or1k_tap_vjtag.c
@@ -218,9 +218,9 @@ static int or1k_tap_vjtag_init(struct or1k_jtag *jtag_info)
 	LOG_DEBUG("SLD HUB Configuration register");
 	LOG_DEBUG("------------------------------");
 	LOG_DEBUG("m_width         = %d", m_width);
-	LOG_DEBUG("manufacturer_id = 0x%02x", MANUF(hub_info));
+	LOG_DEBUG("manufacturer_id = 0x%02" PRIx32, MANUF(hub_info));
 	LOG_DEBUG("nb_of_node      = %d", nb_nodes);
-	LOG_DEBUG("version         = %d", VER(hub_info));
+	LOG_DEBUG("version         = %" PRId32, VER(hub_info));
 	LOG_DEBUG("VIR length      = %d", guess_addr_width(nb_nodes) + m_width);
 
 	/* Because the number of SLD nodes is now known, the Nodes on the hub can be
@@ -259,11 +259,11 @@ static int or1k_tap_vjtag_init(struct or1k_jtag *jtag_info)
 
 		LOG_DEBUG("Node info register");
 		LOG_DEBUG("--------------------");
-		LOG_DEBUG("instance_id     = %d", ID(node_info));
-		LOG_DEBUG("manufacturer_id = 0x%02x", MANUF(node_info));
-		LOG_DEBUG("node_id         = %d (%s)", ID(node_info),
+		LOG_DEBUG("instance_id     = %" PRId32, ID(node_info));
+		LOG_DEBUG("manufacturer_id = 0x%02" PRIx32, MANUF(node_info));
+		LOG_DEBUG("node_id         = %" PRId32 " (%s)", ID(node_info),
 						       id_to_string(ID(node_info)));
-		LOG_DEBUG("version         = %d", VER(node_info));
+		LOG_DEBUG("version         = %" PRId32, VER(node_info));
 
 		if (ID(node_info) == VJTAG_NODE_ID)
 			vjtag_node_address = node_index + 1;