diff options
| author | Salvador Arroyo <sarroyofdez@yahoo.es> | 2012-11-01 15:45:12 +0100 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2012-11-16 12:40:34 +0000 |
| commit | 9aad563d15da07fdd938014e65c1bbc38fcf3f6c (patch) | |
| tree | dcd1a8e8dfc70582267075ace61ba98cab38464d /src/target/mips_m4k.c | |
| parent | 47d5f44fe0401746b3239ea43994889c41c0ca5e (diff) | |
mips: code clean up in mips_m4k_debug_entry() function
The function mips_ejtag_read_debug() is defined in mips_ejtag.c
and is called only by mips_m4k_debug_entry() for reading the
CP0 debug register. The comment in this function is obviously wrong.
There is a generic function to read CP0 registers with similar code.
A call to mips32_cp0_read() should work in the same way.
The purpose of reading the debug register is to test if the DSS
bit is set and clear the SSt bit.
It is faster and easier if the SSt bit is cleared without any check.
Remark: DSS bit set only means that a debug single-step exception
ocurred, but it is not possible to step over a sdbbp instruction,
in this case DSS will not be set and the SSt bit not cleared by code.
Resume command at another address will step, so really the behavior
is not the same.
Change-Id: Ibd35f80e0f7669976d96f4ed813830cecf587971
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/950
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'src/target/mips_m4k.c')
| -rw-r--r-- | src/target/mips_m4k.c | 11 |
1 files changed, 2 insertions, 9 deletions
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c index 1a10d5a9..9a3d929c 100644 --- a/src/target/mips_m4k.c +++ b/src/target/mips_m4k.c @@ -82,10 +82,9 @@ static int mips_m4k_debug_entry(struct target *target) { struct mips32_common *mips32 = target_to_mips32(target); struct mips_ejtag *ejtag_info = &mips32->ejtag_info; - uint32_t debug_reg; - /* read debug register */ - mips_ejtag_read_debug(ejtag_info, &debug_reg); + /* make sure stepping disabled, SSt bit in CP0 debug register cleared */ + mips_ejtag_config_step(ejtag_info, 0); /* make sure break unit configured */ mips32_configure_break_unit(target); @@ -93,12 +92,6 @@ static int mips_m4k_debug_entry(struct target *target) /* attempt to find halt reason */ mips_m4k_examine_debug_reason(target); - /* clear single step if active */ - if (debug_reg & EJTAG_DEBUG_DSS) { - /* stopped due to single step - clear step bit */ - mips_ejtag_config_step(ejtag_info, 0); - } - mips32_save_context(target); /* default to mips32 isa, it will be changed below if required */ |