diff options
author | zwelch <zwelch@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-06-23 22:36:11 +0000 |
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committer | zwelch <zwelch@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-06-23 22:36:11 +0000 |
commit | 50c086ffb94f199c088f4cc52b7887b668dddf00 (patch) | |
tree | f82cbcc5acf534e762fa623923c2b39de0fc07cd /src/target/mips32_dmaacc.c | |
parent | e43979e7020ea9d05a3c0a2af444f292eacb6c53 (diff) |
- Replace 'while(' with 'while ('.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2358 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/mips32_dmaacc.c')
-rw-r--r-- | src/target/mips32_dmaacc.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/target/mips32_dmaacc.c b/src/target/mips32_dmaacc.c index 9727f4e8..cd73d6e2 100644 --- a/src/target/mips32_dmaacc.c +++ b/src/target/mips32_dmaacc.c @@ -61,7 +61,7 @@ begin_ejtag_dma_read: do { ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - } while(ejtag_ctrl & EJTAG_CTRL_DSTRT); + } while (ejtag_ctrl & EJTAG_CTRL_DSTRT); /* Read Data */ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); @@ -107,7 +107,7 @@ begin_ejtag_dma_read_h: do { ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - } while(ejtag_ctrl & EJTAG_CTRL_DSTRT); + } while (ejtag_ctrl & EJTAG_CTRL_DSTRT); /* Read Data */ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); @@ -159,7 +159,7 @@ begin_ejtag_dma_read_b: do { ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - } while(ejtag_ctrl & EJTAG_CTRL_DSTRT); + } while (ejtag_ctrl & EJTAG_CTRL_DSTRT); /* Read Data */ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); @@ -226,7 +226,7 @@ begin_ejtag_dma_write: do { ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - } while(ejtag_ctrl & EJTAG_CTRL_DSTRT); + } while (ejtag_ctrl & EJTAG_CTRL_DSTRT); /* Clear DMA & Check DERR */ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); @@ -277,7 +277,7 @@ begin_ejtag_dma_write_h: do { ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - } while(ejtag_ctrl & EJTAG_CTRL_DSTRT); + } while (ejtag_ctrl & EJTAG_CTRL_DSTRT); /* Clear DMA & Check DERR */ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); @@ -329,7 +329,7 @@ begin_ejtag_dma_write_b: do { ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - } while(ejtag_ctrl & EJTAG_CTRL_DSTRT); + } while (ejtag_ctrl & EJTAG_CTRL_DSTRT); /* Clear DMA & Check DERR */ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); |