diff options
author | drath <drath@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2007-04-26 14:41:27 +0000 |
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committer | drath <drath@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2007-04-26 14:41:27 +0000 |
commit | 2f7eca470778c8b3ba3da698206f69e27c67e54b (patch) | |
tree | e8ce158b0bd1c74dae061bd5dafee60a699b04c8 /src/target/etb.c | |
parent | 22bc5194ae101282cf5c30d681d7f4720bec2534 (diff) |
- improved ETB trace output
- use BKPT instruction on cores supporting it (ARM926EJ-S, ARM966E-S)
- correctly handle endianness of software breakpoint instruction
git-svn-id: svn://svn.berlios.de/openocd/trunk@143 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/etb.c')
-rw-r--r-- | src/target/etb.c | 25 |
1 files changed, 20 insertions, 5 deletions
diff --git a/src/target/etb.c b/src/target/etb.c index 0b480e39..e6c4a851 100644 --- a/src/target/etb.c +++ b/src/target/etb.c @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2005 by Dominic Rath * + * Copyright (C) 2007 by Dominic Rath * * Dominic.Rath@gmx.de * * * * This program is free software; you can redistribute it and/or modify * @@ -341,6 +341,8 @@ int handle_arm7_9_etb_dump_command(struct command_context_s *cmd_ctx, char *cmd, armv4_5_common_t *armv4_5; arm7_9_common_t *arm7_9; int i; + int first_frame = 0; + int last_frame; if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK) { @@ -365,16 +367,29 @@ int handle_arm7_9_etb_dump_command(struct command_context_s *cmd_ctx, char *cmd, arm7_9->etb->RAM_width = buf_get_u32(arm7_9->etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32); } - /* always start reading from the beginning of the buffer */ - etb_write_reg(&arm7_9->etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], 0x0); - for (i = 0; i < arm7_9->etb->RAM_depth; i++) + etb_read_reg(&arm7_9->etb->reg_cache->reg_list[ETB_STATUS]); + etb_read_reg(&arm7_9->etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER]); + + /* check if we overflowed, and adjust first and last frame of the trace accordingly */ + if (buf_get_u32(arm7_9->etb->reg_cache->reg_list[ETB_STATUS].value, 1, 1)) + { + first_frame = buf_get_u32(arm7_9->etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32); + last_frame = first_frame - 1; + } + else + { + last_frame = buf_get_u32(arm7_9->etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32) - 1; + } + + etb_write_reg(&arm7_9->etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame); + for (i = first_frame; (i % arm7_9->etb->RAM_depth) != last_frame; i++) { u32 trace_data; etb_read_reg(&arm7_9->etb->reg_cache->reg_list[ETB_RAM_DATA]); jtag_execute_queue(); trace_data = buf_get_u32(arm7_9->etb->reg_cache->reg_list[ETB_RAM_DATA].value, 0, 32); command_print(cmd_ctx, "%8.8i: %i %2.2x %2.2x %2.2x (0x%8.8x)", - i, (trace_data >> 19) & 1, (trace_data >> 11) & 0xff, (trace_data >> 3) & 0xff, trace_data & 0x7, trace_data); + i % 2048, (trace_data >> 19) & 1, (trace_data >> 11) & 0xff, (trace_data >> 3) & 0xff, trace_data & 0x7, trace_data); } return ERROR_OK; |