diff options
author | drath <drath@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2007-06-21 13:15:22 +0000 |
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committer | drath <drath@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2007-06-21 13:15:22 +0000 |
commit | ffb51c23fdd753ada2554b8b6283533089153b46 (patch) | |
tree | f456f6ad7034d245251ec9e50bc223c1a693bc8b /src/target/embeddedice.c | |
parent | ee01d049089d5be099b84f8974f00f389eaea49b (diff) |
- added support for Intel/Marvel PXA27x (XScale) targets
- added support for scans coming from or ending in Shift-DR or Shift-IR to bitbang code (required for XScale debugging)
- cleaned up errror handlers. only use when there's a catchable error
- fix segfault when etm was configured without a valid driver
git-svn-id: svn://svn.berlios.de/openocd/trunk@176 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/embeddedice.c')
-rw-r--r-- | src/target/embeddedice.c | 19 |
1 files changed, 1 insertions, 18 deletions
diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c index ef38e136..f601c1eb 100644 --- a/src/target/embeddedice.c +++ b/src/target/embeddedice.c @@ -86,15 +86,6 @@ int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf); int embeddedice_write_reg(reg_t *reg, u32 value); int embeddedice_read_reg(reg_t *reg); -int embeddedice_jtag_error_handler(u8 *in_value, void *priv) -{ - char *caller = priv; - - DEBUG("caller: %s", caller); - - return ERROR_OK; -} - reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9) { reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t)); @@ -223,17 +214,13 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) embeddedice_reg_t *ice_reg = reg->arch_info; u8 reg_addr = ice_reg->addr & 0x1f; scan_field_t fields[3]; - error_handler_t error_handler; DEBUG("%i", ice_reg->addr); jtag_add_end_state(TAP_RTI); arm_jtag_scann(ice_reg->jtag_info, 0x2); - error_handler.error_handler = embeddedice_jtag_error_handler; - error_handler.error_handler_priv = "embeddedice_read_reg_w_check"; - - arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, &error_handler); + arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL); fields[0].device = ice_reg->jtag_info->chain_pos; fields[0].num_bits = 32; @@ -324,16 +311,12 @@ int embeddedice_write_reg(reg_t *reg, u32 value) embeddedice_reg_t *ice_reg = reg->arch_info; u8 reg_addr = ice_reg->addr & 0x1f; scan_field_t fields[3]; - error_handler_t error_handler; DEBUG("%i: 0x%8.8x", ice_reg->addr, value); jtag_add_end_state(TAP_RTI); arm_jtag_scann(ice_reg->jtag_info, 0x2); - error_handler.error_handler = embeddedice_jtag_error_handler; - error_handler.error_handler_priv = "embeddedice_write_reg"; - arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL); fields[0].device = ice_reg->jtag_info->chain_pos; |