diff options
author | Rodrigo L. Rosa <rodrigorosa.lg@gmail.com> | 2011-06-10 12:23:34 -0700 |
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committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2011-06-12 11:18:27 +0200 |
commit | 7b0ead520dcf6969954f42255a01e63b89f96cd6 (patch) | |
tree | 1046a2ae0f00e3deefc52ec8c31a26c18bff12ad /src/target/dsp5680xx.h | |
parent | f4b9a2fc8bbc682e957276a0012199a606c919b0 (diff) |
cleanup trailing whitespaces
Diffstat (limited to 'src/target/dsp5680xx.h')
-rw-r--r-- | src/target/dsp5680xx.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/target/dsp5680xx.h b/src/target/dsp5680xx.h index da494c9a..50ab9907 100644 --- a/src/target/dsp5680xx.h +++ b/src/target/dsp5680xx.h @@ -114,13 +114,13 @@ #define DSP5680XX_ONCE_OPDBR 0x08 /* EOnCE Program Data Bus Register (OPDBR) */ #define DSP5680XX_ONCE_OTX1 0x09 /* EOnCE Upper Transmit register (OTX1) */ #define DSP5680XX_ONCE_OPABFR 0x0A /* OnCE Program Address Register—Fetch cycle */ -#define DSP5680XX_ONCE_ORX 0x0B /* EOnCE Receive register (ORX) */ +#define DSP5680XX_ONCE_ORX 0x0B /* EOnCE Receive register (ORX) */ #define DSP5680XX_ONCE_OCNTR_C 0x0C /* Clear OCNTR */ #define DSP5680XX_ONCE_ORX1 0x0D /* EOnCE Upper Receive register (ORX1) */ #define DSP5680XX_ONCE_OTBCR 0x0E /* EOnCE Trace Buffer Control Reg (OTBCR) */ #define DSP5680XX_ONCE_OPABER 0x10 /* OnCE Program Address Register—Execute cycle */ #define DSP5680XX_ONCE_OPFIFO 0x11 /* OnCE Program address FIFO */ -#define DSP5680XX_ONCE_OBAR1 0x12 /* EOnCE Breakpoint 1 Unit 0 Address Reg.(OBAR1) */ +#define DSP5680XX_ONCE_OBAR1 0x12 /* EOnCE Breakpoint 1 Unit 0 Address Reg.(OBAR1) */ #define DSP5680XX_ONCE_OPABDR 0x13 /* OnCE Program Address Register—Decode cycle (OPABDR) */ //---------------------------------------------------------------- @@ -179,7 +179,7 @@ //---------------------------------------------------------------- #define MC568013_EONCE_OBASE_ADDR 0xFF // The following are relative to EONCE_OBASE_ADDR (EONCE_OBASE_ADDR<<16 + ...) -#define MC568013_EONCE_TX_RX_ADDR 0xFFFE // +#define MC568013_EONCE_TX_RX_ADDR 0xFFFE // #define MC568013_EONCE_TX1_RX1_HIGH_ADDR 0xFFFF // Relative to EONCE_OBASE_ADDR #define MC568013_EONCE_OCR 0xFFA0 // Relative to EONCE_OBASE_ADDR //---------------------------------------------------------------- |