stlink: add SWO tracing support

Enable reading the SWO trace output via STLinkv2 dongles that support
it.

This adds an optional initialization parameter "trace" with which the user
specifies a destination file where SWO trace output is appended as it comes in
as well as the trace module's source clock rate.

STLink will be configured for a 2MHz SWO data rate (STLink's highest
supported rate) if the source clock is > 2MHz, otherwise the source
clock is used as the data rate directly.

For example:

trace swo.log 168000000

If "trace" is specified with a usable file path, the stlink_usb driver will
attempt to configure and read SWO trace data as follows:
- on _run(), the target's TPI and TMI are configured and the STLinkv2 is told
  to enable tracing.  Only generic ARM TPI and TMI registers are
  configured, any MCU-specific settings (ex: pin routing) are the
  responsibility of the target firmware.  The configuration applied is
  based on the STLinkv2's capabilities (UART emulation).
- on _v2_get_status(), the trace data (if any) is fetched from the
  STLink after the target status is checked and the target is found to
  be running.
- on _halt(), the STLink is told to disable tracing.

When fetching trace data, the entire trace frame is written to the output file
and that data is flushed.  An external tool may be used to parse the
trace data into a more human-readable format.

Tested on ARM Cortex M4F and M3 MCUs (STM32F407 and STM32L152).

Change-Id: Ic3983d46c82ba77010c23b0e18ce7b275d917f12
Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-on: http://openocd.zylin.com/1524
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>

1 files changed, 13 insertions, 0 deletions

diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index 4452b98b..cdda0faf 100644
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -33,6 +33,11 @@
 
 #define SYSTEM_CONTROL_BASE 0x400FE000
 
+#define ITM_TER		0xE0000E00
+#define ITM_TPR		0xE0000E40
+#define ITM_TCR		0xE0000E80
+#define ITM_LAR		0xE0000FB0
+
 #define CPUID		0xE000ED00
 /* Debug Control Block */
 #define DCB_DHCSR	0xE000EDF0
@@ -64,6 +69,14 @@
 #define FPU_FPCAR	0xE000EF38
 #define FPU_FPDSCR	0xE000EF3C
 
+#define TPI_SSPSR	0xE0040000
+#define TPI_CSPSR	0xE0040004
+#define TPI_ACPR	0xE0040010
+#define TPI_SPPR	0xE00400F0
+#define TPI_FFSR	0xE0040300
+#define TPI_FFCR	0xE0040304
+#define TPI_FSCR	0xE0040308
+
 /* DCB_DHCSR bit and field definitions */
 #define DBGKEY		(0xA05F << 16)
 #define C_DEBUGEN	(1 << 0)