diff options
| author | Spencer Oliver <spen@spen-soft.co.uk> | 2013-08-05 17:46:09 +0100 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2013-09-08 16:13:51 +0000 |
| commit | 83f1c6f9169bdae920ce18108590d8dffad99126 (patch) | |
| tree | 369224d53f594ade8d4c40c9ade953c886ec1363 /src/target/cortex_m.c | |
| parent | 32ac9c0144f7aa7233b941bf78139eef8332fbc2 (diff) | |
armv7m: use consistent arm.cpsr member
We already set cpsr in armv7m_build_reg_cache, so lets use it for all other
accesses to this field.
Change-Id: I19b3b21ecf1571bbea12e1be664845e6544f6fa1
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1539
Tested-by: jenkins
Diffstat (limited to 'src/target/cortex_m.c')
| -rw-r--r-- | src/target/cortex_m.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index 1d08c95f..fbe635bd 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -430,7 +430,7 @@ static int cortex_m3_debug_entry(struct target *target) arm->read_core_reg(target, r, i, ARM_MODE_ANY); } - r = arm->core_cache->reg_list + ARMV7M_xPSR; + r = arm->cpsr; xPSR = buf_get_u32(r->value, 0, 32); #ifdef ARMV7_GDB_HACKS @@ -732,7 +732,7 @@ static int cortex_m3_resume(struct target *target, int current, r->valid = true; /* Make sure we are in Thumb mode */ - r = armv7m->arm.core_cache->reg_list + ARMV7M_xPSR; + r = armv7m->arm.cpsr; buf_set_u32(r->value, 24, 1, 1); r->dirty = true; r->valid = true; |