diff options
author | Andreas Fritiofson <andreas.fritiofson@gmail.com> | 2015-12-28 18:43:22 +0100 |
---|---|---|
committer | Andreas Fritiofson <andreas.fritiofson@gmail.com> | 2015-12-29 20:31:19 +0000 |
commit | 4a7bb931e37e54e8b0cd9d3a6b41c693d1042106 (patch) | |
tree | e73fb44b06e2ac35193f09961791aec919e144c8 /src/target/cortex_m.c | |
parent | 4da8915fb93369cfe21a86ff208813736cf9d9d9 (diff) |
arm_adi_v5: Remove all mem_ap_sel_* functions
All mem_ap_* functions now make sure the SELECT register is updated with
the AP number that it's operating on. This shouldn't have to be handled
explicitly.
Change-Id: Ib193d8930fabb6a25715064355f98258c9580b5d
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3153
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Diffstat (limited to 'src/target/cortex_m.c')
-rw-r--r-- | src/target/cortex_m.c | 104 |
1 files changed, 52 insertions, 52 deletions
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index ca230f37..b813bd7e 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -73,16 +73,16 @@ static int cortexm_dap_read_coreregister_u32(struct target *target, /* because the DCB_DCRDR is used for the emulated dcc channel * we have to save/restore the DCB_DCRDR when used */ if (target->dbg_msg_enabled) { - retval = mem_ap_sel_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr); + retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr); if (retval != ERROR_OK) return retval; } - retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DCRSR, regnum); + retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regnum); if (retval != ERROR_OK) return retval; - retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR, value); + retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR, value); if (retval != ERROR_OK) return retval; @@ -90,7 +90,7 @@ static int cortexm_dap_read_coreregister_u32(struct target *target, /* restore DCB_DCRDR - this needs to be in a separate * transaction otherwise the emulated DCC channel breaks */ if (retval == ERROR_OK) - retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr); + retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr); } return retval; @@ -106,16 +106,16 @@ static int cortexm_dap_write_coreregister_u32(struct target *target, /* because the DCB_DCRDR is used for the emulated dcc channel * we have to save/restore the DCB_DCRDR when used */ if (target->dbg_msg_enabled) { - retval = mem_ap_sel_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr); + retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr); if (retval != ERROR_OK) return retval; } - retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DCRDR, value); + retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, value); if (retval != ERROR_OK) return retval; - retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regnum | DCRSR_WnR); + retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regnum | DCRSR_WnR); if (retval != ERROR_OK) return retval; @@ -123,7 +123,7 @@ static int cortexm_dap_write_coreregister_u32(struct target *target, /* restore DCB_DCRDR - this needs to be in a seperate * transaction otherwise the emulated DCC channel breaks */ if (retval == ERROR_OK) - retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr); + retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr); } return retval; @@ -140,7 +140,7 @@ static int cortex_m_write_debug_halt_mask(struct target *target, /* create new register mask */ cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on; - return mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr); + return mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr); } static int cortex_m_clear_halt(struct target *target) @@ -153,12 +153,12 @@ static int cortex_m_clear_halt(struct target *target) cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP); /* Read Debug Fault Status Register */ - retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr); + retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr); if (retval != ERROR_OK) return retval; /* Clear Debug Fault Status */ - retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr); + retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr); if (retval != ERROR_OK) return retval; LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr); @@ -181,12 +181,12 @@ static int cortex_m_single_step_core(struct target *target) * HALT can put the core into an unknown state. */ if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) { - retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, + retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN); if (retval != ERROR_OK) return retval; } - retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, + retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN); if (retval != ERROR_OK) return retval; @@ -229,22 +229,22 @@ static int cortex_m_endreset_event(struct target *target) struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list; /* REVISIT The four debug monitor bits are currently ignored... */ - retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr); + retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr); if (retval != ERROR_OK) return retval; LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr); /* this register is used for emulated dcc channel */ - retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DCRDR, 0); + retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0); if (retval != ERROR_OK) return retval; /* Enable debug requests */ - retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr); + retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr); if (retval != ERROR_OK) return retval; if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) { - retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_DEBUGEN); + retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_DEBUGEN); if (retval != ERROR_OK) return retval; } @@ -259,7 +259,7 @@ static int cortex_m_endreset_event(struct target *target) * choices *EXCEPT* explicitly scripted overrides like "vector_catch" * or manual updates to the NVIC SHCSR and CCR registers. */ - retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr); + retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr); if (retval != ERROR_OK) return retval; @@ -305,7 +305,7 @@ static int cortex_m_endreset_event(struct target *target) register_cache_invalidate(armv7m->arm.core_cache); /* make sure we have latest dhcsr flags */ - retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr); + retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr); return retval; } @@ -341,47 +341,47 @@ static int cortex_m_examine_exception_reason(struct target *target) struct adiv5_dap *swjdp = armv7m->arm.dap; int retval; - retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr); + retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr); if (retval != ERROR_OK) return retval; switch (armv7m->exception_number) { case 2: /* NMI */ break; case 3: /* Hard Fault */ - retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr); + retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr); if (retval != ERROR_OK) return retval; if (except_sr & 0x40000000) { - retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr); + retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr); if (retval != ERROR_OK) return retval; } break; case 4: /* Memory Management */ - retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr); + retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr); if (retval != ERROR_OK) return retval; - retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar); + retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar); if (retval != ERROR_OK) return retval; break; case 5: /* Bus Fault */ - retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr); + retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr); if (retval != ERROR_OK) return retval; - retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar); + retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar); if (retval != ERROR_OK) return retval; break; case 6: /* Usage Fault */ - retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr); + retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr); if (retval != ERROR_OK) return retval; break; case 11: /* SVCall */ break; case 12: /* Debug Monitor */ - retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr); + retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr); if (retval != ERROR_OK) return retval; break; @@ -415,7 +415,7 @@ static int cortex_m_debug_entry(struct target *target) LOG_DEBUG(" "); cortex_m_clear_halt(target); - retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr); + retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr); if (retval != ERROR_OK) return retval; @@ -492,7 +492,7 @@ static int cortex_m_poll(struct target *target) struct armv7m_common *armv7m = &cortex_m->armv7m; /* Read from Debug Halting Control and Status Register */ - retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr); + retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr); if (retval != ERROR_OK) { target->state = TARGET_UNKNOWN; return retval; @@ -513,7 +513,7 @@ static int cortex_m_poll(struct target *target) detected_failure = ERROR_FAIL; /* refresh status bits */ - retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr); + retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr); if (retval != ERROR_OK) return retval; } @@ -628,13 +628,13 @@ static int cortex_m_soft_reset_halt(struct target *target) LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead."); /* Enter debug state on reset; restore DEMCR in endreset_event() */ - retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DEMCR, + retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET); if (retval != ERROR_OK) return retval; /* Request a core-only reset */ - retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, + retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_VECTRESET); if (retval != ERROR_OK) return retval; @@ -644,9 +644,9 @@ static int cortex_m_soft_reset_halt(struct target *target) register_cache_invalidate(cortex_m->armv7m.arm.core_cache); while (timeout < 100) { - retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr); + retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr); if (retval == ERROR_OK) { - retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, + retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr); if (retval != ERROR_OK) return retval; @@ -889,7 +889,7 @@ static int cortex_m_step(struct target *target, int current, /* Wait for pending handlers to complete or timeout */ do { - retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, + retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr); if (retval != ERROR_OK) { @@ -924,7 +924,7 @@ static int cortex_m_step(struct target *target, int current, } } - retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr); + retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr); if (retval != ERROR_OK) return retval; @@ -991,11 +991,11 @@ static int cortex_m_assert_reset(struct target *target) /* Enable debug requests */ int retval; - retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr); + retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr); if (retval != ERROR_OK) return retval; if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) { - retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_DEBUGEN); + retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_DEBUGEN); if (retval != ERROR_OK) return retval; } @@ -1003,19 +1003,19 @@ static int cortex_m_assert_reset(struct target *target) /* If the processor is sleeping in a WFI or WFE instruction, the * C_HALT bit must be asserted to regain control */ if (cortex_m->dcb_dhcsr & S_SLEEP) { - retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN); + retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN); if (retval != ERROR_OK) return retval; } - retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DCRDR, 0); + retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0); if (retval != ERROR_OK) return retval; if (!target->reset_halt) { /* Set/Clear C_MASKINTS in a separate operation */ if (cortex_m->dcb_dhcsr & C_MASKINTS) { - retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, + retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT); if (retval != ERROR_OK) return retval; @@ -1033,7 +1033,7 @@ static int cortex_m_assert_reset(struct target *target) * bad vector table entries. Should this include MMERR or * other flags too? */ - retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR, + retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET); if (retval != ERROR_OK) return retval; @@ -1057,7 +1057,7 @@ static int cortex_m_assert_reset(struct target *target) "handler to reset any peripherals or configure hardware srst support."); } - retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, + retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ) ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET)); if (retval != ERROR_OK) @@ -1075,7 +1075,7 @@ static int cortex_m_assert_reset(struct target *target) * after reset) on LM3S6918 -- Michael Schwingen */ uint32_t tmp; - retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp); + retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp); if (retval != ERROR_OK) return retval; } @@ -1669,7 +1669,7 @@ static int cortex_m_read_memory(struct target *target, uint32_t address, return ERROR_TARGET_UNALIGNED_ACCESS; } - return mem_ap_sel_read_buf(armv7m->debug_ap, buffer, size, count, address); + return mem_ap_read_buf(armv7m->debug_ap, buffer, size, count, address); } static int cortex_m_write_memory(struct target *target, uint32_t address, @@ -1683,7 +1683,7 @@ static int cortex_m_write_memory(struct target *target, uint32_t address, return ERROR_TARGET_UNALIGNED_ACCESS; } - return mem_ap_sel_write_buf(armv7m->debug_ap, buffer, size, count, address); + return mem_ap_write_buf(armv7m->debug_ap, buffer, size, count, address); } static int cortex_m_init_target(struct command_context *cmd_ctx, @@ -2025,7 +2025,7 @@ static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctr uint8_t buf[2]; int retval; - retval = mem_ap_sel_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR); + retval = mem_ap_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR); if (retval != ERROR_OK) return retval; @@ -2039,7 +2039,7 @@ static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctr * signify we have read data */ if (dcrdr & (1 << 0)) { target_buffer_set_u16(target, buf, 0); - retval = mem_ap_sel_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR); + retval = mem_ap_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR); if (retval != ERROR_OK) return retval; } @@ -2194,7 +2194,7 @@ COMMAND_HANDLER(handle_cortex_m_vector_catch_command) if (retval != ERROR_OK) return retval; - retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr); + retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr); if (retval != ERROR_OK) return retval; @@ -2231,10 +2231,10 @@ write: demcr |= catch; /* write, but don't assume it stuck (why not??) */ - retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr); + retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr); if (retval != ERROR_OK) return retval; - retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr); + retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr); if (retval != ERROR_OK) return retval; |