diff options
| author | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-22 10:21:48 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-22 10:27:29 -0800 |
| commit | b404b9ab57f17d84eb8dbfb42e6ac49c32913eee (patch) | |
| tree | 4416b9f407908e7554dc8b2f5329c4461dfa9516 /src/target/cortex_a8.c | |
| parent | fa618cc74deea6741c745b4f80dace2421209a1e (diff) | |
ARM: use arm_reg_current()
Start using the arm_reg_current() call. This shrinks and speeds
the affected code. It can also prevent some coredumps coming from
invalid CPSR values ... the ARMV4_5_CORE_REG_MODE() macro returns
bogus registers if e.g. "Secure Monitor" mode isn't supported by
the current CPU.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target/cortex_a8.c')
| -rw-r--r-- | src/target/cortex_a8.c | 24 |
1 files changed, 8 insertions, 16 deletions
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c index de579feb..b006e81a 100644 --- a/src/target/cortex_a8.c +++ b/src/target/cortex_a8.c @@ -496,8 +496,7 @@ static int cortex_a8_resume(struct target *target, int current, /* current = 1: continue on current pc, otherwise continue at <address> */ resume_pc = buf_get_u32( - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, - armv4_5->core_mode, 15).value, + armv4_5->core_cache->reg_list[15].value, 0, 32); if (!current) resume_pc = address; @@ -522,13 +521,10 @@ static int cortex_a8_resume(struct target *target, int current, return ERROR_FAIL; } LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc); - buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, - armv4_5->core_mode, 15).value, + buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, resume_pc); - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, - armv4_5->core_mode, 15).dirty = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, - armv4_5->core_mode, 15).valid = 1; + armv4_5->core_cache->reg_list[15].dirty = 1; + armv4_5->core_cache->reg_list[15].valid = 1; cortex_a8_restore_context(target); @@ -653,8 +649,7 @@ static int cortex_a8_debug_entry(struct target *target) /* update cache */ for (i = 0; i <= ARM_PC; i++) { - reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, - armv4_5->core_mode, i); + reg = arm_reg_current(armv4_5, i); buf_set_u32(reg->value, 0, 32, regfile[i]); reg->valid = 1; @@ -672,13 +667,10 @@ static int cortex_a8_debug_entry(struct target *target) // ARM state regfile[ARM_PC] -= 8; } - buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, - armv4_5->core_mode, ARM_PC).value, - 0, 32, regfile[ARM_PC]); - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0) - .dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, - armv4_5->core_mode, 0).valid; + reg = armv4_5->core_cache->reg_list + 15; + buf_set_u32(reg->value, 0, 32, regfile[ARM_PC]); + reg->dirty = reg->valid; ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15) .dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid; |