diff options
| author | Andrey Smirnov <andrew.smirnov@gmail.com> | 2015-08-08 15:18:16 -0700 |
|---|---|---|
| committer | Freddie Chopin <freddie.chopin@gmail.com> | 2016-11-04 21:21:50 +0000 |
| commit | d1bdcdcc8d429a2ce06fb35f82a67b2487b72ec3 (patch) | |
| tree | 10ee3d0066d25458de15347ab5c23aa07c646089 /src/target/cortex_a.c | |
| parent | b10037a0b784cab94e21b37c976ad2b5174d52ae (diff) | |
semihosting armv7a: Add support for ARMv7-A
Add semihosting support for ARMv7-A based processors.
Tested with custom Vybrid VF610 based board
and Pandaboard ES (Rev. B1) board (Cortex-A9).
Change-Id: I6b896a61c1c6a1c5dcf89de834486f82dd6c80a2
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Tsung-Han Lin <tsunghan.tw@gmail.com>
Reviewed-on: http://openocd.zylin.com/2908
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
Diffstat (limited to 'src/target/cortex_a.c')
| -rw-r--r-- | src/target/cortex_a.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index d1590f65..0a689eaf 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -53,6 +53,7 @@ #include "target_request.h" #include "target_type.h" #include "arm_opcodes.h" +#include "arm_semihosting.h" #include <helper/time_support.h> static int cortex_a_poll(struct target *target); @@ -915,6 +916,10 @@ static int cortex_a_poll(struct target *target) if (retval != ERROR_OK) return retval; } + + if (arm_semihosting(target, &retval) != 0) + return retval; + target_call_event_callbacks(target, TARGET_EVENT_HALTED); } @@ -1201,7 +1206,7 @@ static int cortex_a_resume(struct target *target, int current, static int cortex_a_debug_entry(struct target *target) { int i; - uint32_t regfile[16], cpsr, dscr; + uint32_t regfile[16], cpsr, spsr, dscr; int retval = ERROR_OK; struct working_area *regfile_working_area = NULL; struct cortex_a_common *cortex_a = target_to_cortex_a(target); @@ -1250,6 +1255,7 @@ static int cortex_a_debug_entry(struct target *target) if (cortex_a->fast_reg_read) target_alloc_working_area(target, 64, ®file_working_area); + /* First load register acessible through core debug port*/ if (!regfile_working_area) retval = arm_dpm_read_current_registers(&armv7a->dpm); @@ -1294,6 +1300,17 @@ static int cortex_a_debug_entry(struct target *target) reg->dirty = reg->valid; } + /* read Saved PSR */ + retval = cortex_a_dap_read_coreregister_u32(target, &spsr, 17); + /* store current spsr */ + if (retval != ERROR_OK) + return retval; + + reg = arm->spsr; + buf_set_u32(reg->value, 0, 32, spsr); + reg->valid = 1; + reg->dirty = 0; + #if 0 /* TODO, Move this */ uint32_t cp15_control_register, cp15_cacr, cp15_nacr; @@ -2953,6 +2970,7 @@ static int cortex_a_examine_first(struct target *target) struct cortex_a_common *cortex_a = target_to_cortex_a(target); struct armv7a_common *armv7a = &cortex_a->armv7a_common; struct adiv5_dap *swjdp = armv7a->arm.dap; + int i; int retval = ERROR_OK; uint32_t didr, ctypr, ttypr, cpuid, dbg_osreg; |