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| author | Matthias Welwarsky <matthias.welwarsky@sysgo.com> | 2016-10-20 11:31:40 +0200 |
|---|---|---|
| committer | Matthias Welwarsky <matthias.welwarsky@sysgo.com> | 2017-02-10 14:18:34 +0100 |
| commit | 946958cb723f0b123505234275ce9a653ddbfbd2 (patch) | |
| tree | 2f1544feb6455fc51c608b1f6cccbc34b7827e91 /src/target/armv8_cache.c | |
| parent | 79c4c22e1570cf0d73bacb4d292951e614d0ab2f (diff) | |
aarch64: fix mode switching
DCPS only allows to enter higher ELs, for lower ELs you need to
use DRPS. Also, of course the encoding differs between A64 and T32.
Both DCPS and DRPS also clobber DLR and DSPSR, which then need to be
restored on resume.
Change-Id: Ifa3dcfa94212702e57170bd59fd0bb25495fb6fd
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Diffstat (limited to 'src/target/armv8_cache.c')
0 files changed, 0 insertions, 0 deletions