diff options
author | zwelch <zwelch@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-07-16 00:08:21 +0000 |
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committer | zwelch <zwelch@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2009-07-16 00:08:21 +0000 |
commit | 16e17ab1b33c8d40cc28bf621fc7995366a28a8a (patch) | |
tree | 21f068ec71cc16f0b25616c3e4c642cb6a6a61b7 /src/target/armv7m.h | |
parent | 0c2ff267aadc8997e2a337d43eb3a3510f2bd2a1 (diff) |
Magnus Lundin <lundin@mlu.mine.nu>, Oyvind Harboe <oyvind.harboe@zylin.com>, David Brownell <david-b@pacbell.net>:
Some cleanup of the ARMv7-M support:
- Reference the relevant ARMv7-M ARM doc (DDI 0405C to non-Vendors), and
update the Cortex-M3 doc refs (DDI 0337C is no longer available).
- Those registers aren't actually general, and some are incorrect (per all
public docs anyway). Update comments and code accordingly.
* What the Core Debug facility exposes is *implementation-specific*
not architectural. These values aren't fully portable. They match
Cortex-M3 ... so no current implementation will make trouble, but
the next v7m implementation might.
* Four of the registers are actually not exposed that way. Before
Cortex-M3 r2p0 they are read/written through MRS/MSR instructions.
In that newest silicon, they are four bytes in one register, not
four separate registers.
- Update the CM3 code to report when that one register is available,
and not try to access it when it isn't. Also declare the register
numbers that an eventual MRS/MSR solution will need to be using.
- Stop line wrapping the exception labels.
So for parts before r2p0 OpenOCD behavior is effectively unchanged, and
still buggy; but for those newer parts a few things might now be correct.
Most current Cortex-M3 parts use r1p1 (or earlier); this seems to include
most LM3S parts and all STM32 parts. Parts using r2p0 are available, and
include fourth generation LM3S parts ("Tempest") plus AT91SAM3 and LPC17xx
parts which are now sampling.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2543 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/armv7m.h')
-rw-r--r-- | src/target/armv7m.h | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/src/target/armv7m.h b/src/target/armv7m.h index ec90b715..17e3ff38 100644 --- a/src/target/armv7m.h +++ b/src/target/armv7m.h @@ -61,10 +61,15 @@ enum ARMV7M_xPSR = 16, ARMV7M_MSP, ARMV7M_PSP, - ARMV7M_PRIMASK, - ARMV7M_BASEPRI, - ARMV7M_FAULTMASK, - ARMV7M_CONTROL, + + /* FIXME the register numbers here are core-specific. Cortex-M3 + * through r1p1 only defines registers up to PSP; see ARM DDI 0337E. + * + * It's r2p0 (see ARM DDI 0337G) which defines the register that's + * called SPEC20 here, with four single-byte fields with CONTROL + * (highest byte), FAULTMASK, BASEPRI, and PRIMASK (lowest byte). + */ + ARMV7M_SPEC20 = 20, ARMV7NUMCOREREGS }; @@ -78,6 +83,7 @@ typedef struct armv7m_common_s int exception_number; swjdp_common_t swjdp_info; + bool has_spec20; /* Direct processor core register read and writes */ int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t *value); |