diff options
author | ntfreak <ntfreak@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-11-20 11:17:47 +0000 |
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committer | ntfreak <ntfreak@b42882b7-edfa-0310-969c-e2dbd0fdcd60> | 2008-11-20 11:17:47 +0000 |
commit | e507bfddb0bfc45dad16ec036df9039ef6666ff9 (patch) | |
tree | 01dfc727cc0f18a5fd6fc4735d608366064536f1 /src/target/armv7m.c | |
parent | cca10e65346f7f34cc2f8943d7635b7fcf039cab (diff) |
- preserve cortex_m3 C_MASKINTS during resume/step
git-svn-id: svn://svn.berlios.de/openocd/trunk@1179 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'src/target/armv7m.c')
-rw-r--r-- | src/target/armv7m.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/target/armv7m.c b/src/target/armv7m.c index 2258967a..d4c6d357 100644 --- a/src/target/armv7m.c +++ b/src/target/armv7m.c @@ -303,14 +303,14 @@ static int armv7m_run_and_wait(struct target_s *target, u32 entry_point, int tim u32 pc; int retval; /* This code relies on the target specific resume() and poll()->debug_entry() - sequence to write register values to the processor and the read them back */ + * sequence to write register values to the processor and the read them back */ if((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK) { return retval; } retval = target_wait_state(target, TARGET_HALTED, timeout_ms); - // If the target fails to halt due to the breakpoint, force a halt + /* If the target fails to halt due to the breakpoint, force a halt */ if (retval != ERROR_OK || target->state != TARGET_HALTED) { if ((retval=target_halt(target))!=ERROR_OK) @@ -322,7 +322,6 @@ static int armv7m_run_and_wait(struct target_s *target, u32 entry_point, int tim return ERROR_TARGET_TIMEOUT; } - armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc); if (pc != exit_point) { |