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author | Antonio Borneo <borneo.antonio@gmail.com> | 2018-12-03 18:50:43 +0100 |
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committer | Matthias Welwarsky <matthias@welwarsky.de> | 2018-12-18 13:22:55 +0000 |
commit | bff87a7f28fb60b40f14a91ed3bef982bdc8db92 (patch) | |
tree | 21f92a0d682333c8751786711cc13e57fc80fb7b /src/target/armv7a_cache.c | |
parent | 322d2fa12c9b5520e06c1d581ce8b4e3c75750ca (diff) |
target/cortex_a: enable DSCR_HALT_DBG_MODE during examine
Arm architecture reference manual DDI0406C reports at page 2024 in
table C3-1 the processor behaviour on debug events depending on
the debug-mode (none, monitor or halt), mode selected through the
bits MDBGen and HDBGen in DSCR register.
The halt request is served independently from the debug-mode. Thus
it's useless to enable the halt debug-mode in cortex_a_halt() by
setting the bit HDBGen (macro DSCR_HALT_DBG_MODE).
On the other side, halting for a breakpoint, a watchpoint or a
vector catch requires being in halt debug-mode.
Today HDBGen is set only in cortex_a_halt(), so we are forced to
halt the core at least once before it can be halted for hitting a
breakpoint/watchpoint/vector-catch. This is annoying since there
is no need to halt the target to set a HW breakpoint.
Move in cortex_a_init_debug_access() the selection of the halt
debug-mode, so the mode is set during examine.
To prevent a misconfigured hardware breakpoint/watchpoint/vector
catch to halt the target when OpenOCD has already quit, return to
debug-mode none at OpenOCD exit.
Change-Id: I68a1c51de3572ca1b89e90caf7eb20374268e926
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4783
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Diffstat (limited to 'src/target/armv7a_cache.c')
0 files changed, 0 insertions, 0 deletions