diff options
author | Spencer Oliver <spen@spen-soft.co.uk> | 2012-02-05 12:03:04 +0000 |
---|---|---|
committer | Spencer Oliver <spen@spen-soft.co.uk> | 2012-02-06 11:00:36 +0000 |
commit | 374127301ec1d72033b9d573b72c7abdfd61990d (patch) | |
tree | b56f5f4bba1718f9ac482d1fabdff18f5d170196 /src/target/armv4_5_mmu.c | |
parent | de0130a0aad83c1ef692ee4d68ab996a8668424d (diff) |
build: cleanup src/target directory
Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/430
Tested-by: jenkins
Diffstat (limited to 'src/target/armv4_5_mmu.c')
-rw-r--r-- | src/target/armv4_5_mmu.c | 67 |
1 files changed, 31 insertions, 36 deletions
diff --git a/src/target/armv4_5_mmu.c b/src/target/armv4_5_mmu.c index 5415e83b..c8dc560c 100644 --- a/src/target/armv4_5_mmu.c +++ b/src/target/armv4_5_mmu.c @@ -17,6 +17,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -25,8 +26,8 @@ #include "target.h" #include "armv4_5_mmu.h" - -int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, uint32_t *cb, uint32_t *val) +int armv4_5_mmu_translate_va(struct target *target, + struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, uint32_t *cb, uint32_t *val) { uint32_t first_lvl_descriptor = 0x0; uint32_t second_lvl_descriptor = 0x0; @@ -34,62 +35,55 @@ int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *a int retval; retval = armv4_5_mmu->get_ttb(target, &ttb); if (retval != ERROR_OK) - return retval; + return retval; retval = armv4_5_mmu_read_physical(target, armv4_5_mmu, (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18), - 4, 1, (uint8_t*)&first_lvl_descriptor); + 4, 1, (uint8_t *)&first_lvl_descriptor); if (retval != ERROR_OK) - return retval; - first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&first_lvl_descriptor); + return retval; + first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)&first_lvl_descriptor); LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor); - if ((first_lvl_descriptor & 0x3) == 0) - { + if ((first_lvl_descriptor & 0x3) == 0) { LOG_ERROR("Address translation failure"); return ERROR_TARGET_TRANSLATION_FAULT; } - if (!armv4_5_mmu->has_tiny_pages && ((first_lvl_descriptor & 0x3) == 3)) - { + if (!armv4_5_mmu->has_tiny_pages && ((first_lvl_descriptor & 0x3) == 3)) { LOG_ERROR("Address translation failure"); return ERROR_TARGET_TRANSLATION_FAULT; } - if ((first_lvl_descriptor & 0x3) == 2) - { + if ((first_lvl_descriptor & 0x3) == 2) { /* section descriptor */ *cb = (first_lvl_descriptor & 0xc) >> 2; *val = (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff); return ERROR_OK; } - if ((first_lvl_descriptor & 0x3) == 1) - { + if ((first_lvl_descriptor & 0x3) == 1) { /* coarse page table */ retval = armv4_5_mmu_read_physical(target, armv4_5_mmu, (first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10), - 4, 1, (uint8_t*)&second_lvl_descriptor); + 4, 1, (uint8_t *)&second_lvl_descriptor); if (retval != ERROR_OK) return retval; - } - else if ((first_lvl_descriptor & 0x3) == 3) - { + } else if ((first_lvl_descriptor & 0x3) == 3) { /* fine page table */ retval = armv4_5_mmu_read_physical(target, armv4_5_mmu, (first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8), - 4, 1, (uint8_t*)&second_lvl_descriptor); + 4, 1, (uint8_t *)&second_lvl_descriptor); if (retval != ERROR_OK) return retval; } - second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&second_lvl_descriptor); + second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)&second_lvl_descriptor); LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor); - if ((second_lvl_descriptor & 0x3) == 0) - { + if ((second_lvl_descriptor & 0x3) == 0) { LOG_ERROR("Address translation failure"); return ERROR_TARGET_TRANSLATION_FAULT; } @@ -97,22 +91,19 @@ int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *a /* cacheable/bufferable is always specified in bits 3-2 */ *cb = (second_lvl_descriptor & 0xc) >> 2; - if ((second_lvl_descriptor & 0x3) == 1) - { + if ((second_lvl_descriptor & 0x3) == 1) { /* large page descriptor */ *val = (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff); return ERROR_OK; } - if ((second_lvl_descriptor & 0x3) == 2) - { + if ((second_lvl_descriptor & 0x3) == 2) { /* small page descriptor */ *val = (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff); return ERROR_OK; } - if ((second_lvl_descriptor & 0x3) == 3) - { + if ((second_lvl_descriptor & 0x3) == 3) { /* tiny page descriptor */ *val = (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff); return ERROR_OK; @@ -123,7 +114,9 @@ int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *a return ERROR_TARGET_TRANSLATION_FAULT; } -int armv4_5_mmu_read_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +int armv4_5_mmu_read_physical(struct target *target, + struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, + uint32_t size, uint32_t count, uint8_t *buffer) { int retval; @@ -132,24 +125,26 @@ int armv4_5_mmu_read_physical(struct target *target, struct armv4_5_mmu_common * /* disable MMU and data (or unified) cache */ retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0); - if (retval !=ERROR_OK) + if (retval != ERROR_OK) return retval; retval = armv4_5_mmu->read_memory(target, address, size, count, buffer); - if (retval !=ERROR_OK) + if (retval != ERROR_OK) return retval; /* reenable MMU / cache */ retval = armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled, armv4_5_mmu->armv4_5_cache.d_u_cache_enabled, armv4_5_mmu->armv4_5_cache.i_cache_enabled); - if (retval !=ERROR_OK) + if (retval != ERROR_OK) return retval; return retval; } -int armv4_5_mmu_write_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer) +int armv4_5_mmu_write_physical(struct target *target, + struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, + uint32_t size, uint32_t count, const uint8_t *buffer) { int retval; @@ -158,18 +153,18 @@ int armv4_5_mmu_write_physical(struct target *target, struct armv4_5_mmu_common /* disable MMU and data (or unified) cache */ retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0); - if (retval !=ERROR_OK) + if (retval != ERROR_OK) return retval; retval = armv4_5_mmu->write_memory(target, address, size, count, buffer); - if (retval !=ERROR_OK) + if (retval != ERROR_OK) return retval; /* reenable MMU / cache */ retval = armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled, armv4_5_mmu->armv4_5_cache.d_u_cache_enabled, armv4_5_mmu->armv4_5_cache.i_cache_enabled); - if (retval !=ERROR_OK) + if (retval != ERROR_OK) return retval; return retval; |