diff options
author | David Brownell <dbrownell@users.sourceforge.net> | 2009-12-04 20:14:46 -0800 |
---|---|---|
committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-12-04 20:14:46 -0800 |
commit | 340e2eb7629fc1fdb6d2ead2952982584abdcefa (patch) | |
tree | 8522b7288d8d8e8e763084d27882d5c7b13662e3 /src/target/armv4_5.h | |
parent | e51b9a4ac7afa0fde11690268ba88861e1000f60 (diff) |
ARM: misc generic cleanup
Remove an undesirable use of the CPSR symbol ... it needs to vanish.
Flag mode-to-number stuff as obsolete; say why ... should also vanish.
Get rid of no-longer-used mode and state typedefs.
Comment a few of the implicit ties to "classic ARM".
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target/armv4_5.h')
-rw-r--r-- | src/target/armv4_5.h | 26 |
1 files changed, 17 insertions, 9 deletions
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h index 6a082a57..b56a1f16 100644 --- a/src/target/armv4_5.h +++ b/src/target/armv4_5.h @@ -30,8 +30,11 @@ #include <helper/command.h> -typedef enum arm_mode -{ +/* These numbers match the five low bits of the *PSR registers on + * "classic ARM" processors, which build on the ARMv4 processor + * modes and register set. + */ +enum arm_mode { ARM_MODE_USR = 16, ARM_MODE_FIQ = 17, ARM_MODE_IRQ = 18, @@ -41,24 +44,29 @@ typedef enum arm_mode ARM_MODE_UND = 27, ARM_MODE_SYS = 31, ARM_MODE_ANY = -1 -} arm_mode_t; +}; const char *arm_mode_name(unsigned psr_mode); bool is_arm_mode(unsigned psr_mode); -int arm_mode_to_number(enum arm_mode mode); -enum arm_mode armv4_5_number_to_mode(int number); - -typedef enum arm_state -{ +/* The PSR "T" and "J" bits define the mode of "classic ARM" cores */ +enum arm_state { ARM_STATE_ARM, ARM_STATE_THUMB, ARM_STATE_JAZELLE, ARM_STATE_THUMB_EE, -} arm_state_t; +}; extern const char *arm_state_strings[]; +/* OBSOLETE, DO NOT USE IN NEW CODE! The "number" of an arm_mode is an + * index into the armv4_5_core_reg_map array. Its remaining users are + * remnants which could as easily walk * the register cache directly as + * use the expensive ARMV4_5_CORE_REG_MODE() macro. + */ +int arm_mode_to_number(enum arm_mode mode); +enum arm_mode armv4_5_number_to_mode(int number); + extern const int armv4_5_core_reg_map[8][17]; #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \ |