diff options
author | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-24 21:24:44 -0800 |
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committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-24 21:24:44 -0800 |
commit | c008d30fe85a674842632e32d732e22e0a91b95d (patch) | |
tree | a2de30f8dd613f9347980406fef10e58563849b6 /src/target/arm_dpm.c | |
parent | 991daa03ebbc69829be4a3899b77efb981254038 (diff) |
Cortex-A8: implement DPM
This implements the DPM interface for Cortex-A8 cores. It
also adds a synchronization operation to the DPM framework,
which is needed by the Cortex-A8 after CPSR writes.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target/arm_dpm.c')
-rw-r--r-- | src/target/arm_dpm.c | 13 |
1 files changed, 4 insertions, 9 deletions
diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c index 18a9dcc7..b8107d78 100644 --- a/src/target/arm_dpm.c +++ b/src/target/arm_dpm.c @@ -52,10 +52,8 @@ static int dpm_modeswitch(struct arm_dpm *dpm, enum armv4_5_mode mode) retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MSR_GP(0, 0xf, 0), cpsr); - /* REVISIT on Cortex-A8, we need a Prefetch Flush operation too ... - cortex_a8_exec_opcode(target, - ARMV4_5_MCR(15, 0, 0, 7, 5, 4)); - */ + if (dpm->instr_cpsr_sync) + retval = dpm->instr_cpsr_sync(dpm); return retval; } @@ -142,11 +140,8 @@ static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum) ARMV4_5_MSR_GP(0, 0xf, regnum & 1), value); - /* REVISIT on Cortex-A8, we need a Prefetch Flush operation - * after writing CPSR ... - cortex_a8_exec_opcode(target, - ARMV4_5_MCR(15, 0, 0, 7, 5, 4)); - */ + if (regnum == 16 && dpm->instr_cpsr_sync) + retval = dpm->instr_cpsr_sync(dpm); break; } |