diff options
| author | Tim Newsome <tim@sifive.com> | 2018-07-18 13:34:23 -0700 |
|---|---|---|
| committer | Matthias Welwarsky <matthias@welwarsky.de> | 2018-07-24 13:07:26 +0100 |
| commit | a51ab8ddf63a0d60eaaf3b8f3eedcada1e773c20 (patch) | |
| tree | 60cd18e3649cbc2700abfe7724954e97de640229 /src/target/Makefile.am | |
| parent | 9363705820d9552bd24a4e876041a90a881ede55 (diff) | |
Add RISC-V support.
This supports both 0.11 and 0.13 versions of the debug spec.
Support for `-rtos riscv` will come in a separate commit since it was
easy to separate out, and is likely to be more controversial.
Flash support for the SiFive boards will also come in a later commit.
Change-Id: I1d38fe669c2041b4e21a5c54a091594aac3e2190
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4578
Tested-by: jenkins
Reviewed-by: Liviu Ionescu <ilg@livius.net>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Diffstat (limited to 'src/target/Makefile.am')
| -rw-r--r-- | src/target/Makefile.am | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/target/Makefile.am b/src/target/Makefile.am index fcc23adb..b1119e7d 100644 --- a/src/target/Makefile.am +++ b/src/target/Makefile.am @@ -4,7 +4,9 @@ else OOCD_TRACE_FILES = endif -%C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la +%C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la \ + %D%/riscv/libriscv.la + STARTUP_TCL_SRCS += %D%/startup.tcl @@ -218,3 +220,4 @@ INTEL_IA32_SRC = \ %D%/arm_cti.h include %D%/openrisc/Makefile.am +include %D%/riscv/Makefile.am |