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| author | Robert Jordens <jordens@gmail.com> | 2015-06-30 17:16:08 -0600 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2015-08-06 13:13:52 +0100 |
| commit | 7aade468437a8b50e231c29c9889b67fe53dbccc (patch) | |
| tree | 7e2146dc373e2d19f45bb931bc0e00bd914a7046 /src/flash/nor | |
| parent | a651f202b26187e36f67ca74d599545ee498a289 (diff) | |
target/testee: manage target->state
The testee target is usefull for certain non-cpu pass-through
situations, for example in the case of a spi flash mapped to the DR of
a JTAG tap, as is the case for most FPGAs with SPI flashs behind them.
We just manage the RUNNING/RESET/HALTED state in the testee driver to
support it being halted which is a requirement for flash banks.
Change-Id: I1b4d52c58a1f6bd753e126bfde74dcc5164d7b69
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/2840
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'src/flash/nor')
0 files changed, 0 insertions, 0 deletions