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authorTim Newsome <tim@sifive.com>2019-02-14 17:33:28 -0800
committerMatthias Welwarsky <matthias@welwarsky.de>2019-03-08 14:05:35 +0000
commitc3b90c052acfb7e35a0f4ce22276d53a96d631c7 (patch)
tree38d260910f37f2213c6c1e3159dcef342ba25923 /src/flash/nor/stm32lx.c
parent57e30102ea440d77aa001e26eb901d0cbb305a30 (diff)
flash/nor: use target_addr_t for flash bank base
This should allow users to configure flash at >32-bit addresses. Change-Id: I7c9d3c5762579011a2d9708e5317e5765349845c Signed-off-by: Tim Newsome <tim@sifive.com> Reviewed-on: http://openocd.zylin.com/4919 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Diffstat (limited to 'src/flash/nor/stm32lx.c')
-rw-r--r--src/flash/nor/stm32lx.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/flash/nor/stm32lx.c b/src/flash/nor/stm32lx.c
index 1be950fe..814df8f6 100644
--- a/src/flash/nor/stm32lx.c
+++ b/src/flash/nor/stm32lx.c
@@ -816,8 +816,9 @@ static int stm32lx_probe(struct flash_bank *bank)
/* This is the first bank */
flash_size_in_kb = stm32lx_info->part_info.first_bank_size_kb;
} else {
- LOG_WARNING("STM32L flash bank base address config is incorrect."
- " 0x%" PRIx32 " but should rather be 0x%" PRIx32 " or 0x%" PRIx32,
+ LOG_WARNING("STM32L flash bank base address config is incorrect. "
+ TARGET_ADDR_FMT " but should rather be 0x%" PRIx32
+ " or 0x%" PRIx32,
bank->base, base_address, second_bank_base);
return ERROR_FAIL;
}