diff options
| author | Andreas Fritiofson <andreas.fritiofson@gmail.com> | 2012-01-25 01:10:24 +0100 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2012-01-30 20:01:42 +0000 |
| commit | 81b4ef6ee52fd0e897f4c2ecc6a173161abb930f (patch) | |
| tree | 7510ae4d6aeae9f02baa0cb4c6fa129b2c334db8 /src/flash/nor/stm32f1x.c | |
| parent | 61f3d4b7e42897fb1570bd4307137833cce0f7ba (diff) | |
stm32f1x: fix bug in flash loader and restrict instruction set to armv6-m
Correct the offset to the read pointer when clearing it on error.
Also restrict the instruction set to armv6-m so the flash driver can be
used on Cortex-M0 parts with the same flash controller.
Change-Id: I380f9dabcc41fb6e4d43a7e02f355e2381913f39
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/399
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-by: Jonathan Dumaresq <jdumaresq@cimeq.qc.ca>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'src/flash/nor/stm32f1x.c')
| -rw-r--r-- | src/flash/nor/stm32f1x.c | 59 |
1 files changed, 33 insertions, 26 deletions
diff --git a/src/flash/nor/stm32f1x.c b/src/flash/nor/stm32f1x.c index b4ec93f6..02ab8c99 100644 --- a/src/flash/nor/stm32f1x.c +++ b/src/flash/nor/stm32f1x.c @@ -635,35 +635,42 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer, /* #define STM32_FLASH_CR_OFFSET 0x10 */ /* #define STM32_FLASH_SR_OFFSET 0x0C */ /* wait_fifo: */ - 0x16, 0x68, /* ldr r6, [r2, #0] */ - 0x00, 0x2e, /* cmp r6, #0 */ - 0x1a, 0xd0, /* beq exit */ - 0x55, 0x68, /* ldr r5, [r2, #4] */ - 0xb5, 0x42, /* cmp r5, r6 */ - 0xf9, 0xd0, /* beq wait_fifo */ - 0x01, 0x26, /* movs r6, #1 */ - 0x06, 0x61, /* str r6, [r0, #STM32_FLASH_CR_OFFSET] */ - 0x35, 0xf8, 0x02, 0x6b, /* ldrh r6, [r5], #2 */ - 0x24, 0xf8, 0x02, 0x6b, /* strh r6, [r4], #2 */ + 0x16, 0x68, /* ldr r6, [r2, #0] */ + 0x00, 0x2e, /* cmp r6, #0 */ + 0x1a, 0xd0, /* beq exit */ + 0x55, 0x68, /* ldr r5, [r2, #4] */ + 0xb5, 0x42, /* cmp r5, r6 */ + 0xf9, 0xd0, /* beq wait_fifo */ + 0x01, 0x26, /* movs r6, #1 */ + 0x06, 0x61, /* str r6, [r0, #STM32_FLASH_CR_OFFSET] */ + 0x2e, 0x88, /* ldrh r6, [r5, #0] */ + 0x26, 0x80, /* strh r6, [r4, #0] */ + 0x02, 0x35, /* adds r5, #2 */ + 0x02, 0x34, /* adds r4, #2 */ /* busy: */ - 0xc6, 0x68, /* ldr r6, [r0, #STM32_FLASH_SR_OFFSET] */ - 0x16, 0xf0, 0x01, 0x0f, /* tst r6, #1 */ - 0xfb, 0xd1, /* bne busy */ - 0x16, 0xf0, 0x14, 0x0f, /* tst r6, #0x14 */ - 0x07, 0xd1, /* bne error */ - 0x9d, 0x42, /* cmp r5, r3 */ - 0x28, 0xbf, /* it cs */ - 0x02, 0xf1, 0x08, 0x05, /* addcs r5, r2, #8 */ - 0x55, 0x60, /* str r5, [r2, #4] */ - 0x01, 0x39, /* subs r1, r1, #1 */ - 0x19, 0xb1, /* cbz r1, exit */ - 0xe4, 0xe7, /* b wait_fifo */ + 0xc6, 0x68, /* ldr r6, [r0, #STM32_FLASH_SR_OFFSET] */ + 0x01, 0x27, /* movs r7, #1 */ + 0x3e, 0x42, /* tst r6, r7 */ + 0xfb, 0xd1, /* bne busy */ + 0x14, 0x27, /* movs r7, #0x14 */ + 0x3e, 0x42, /* tst r6, r7 */ + 0x08, 0xd1, /* bne error */ + 0x9d, 0x42, /* cmp r5, r3 */ + 0x01, 0xd3, /* bcc no_wrap */ + 0x15, 0x46, /* mov r5, r2 */ + 0x08, 0x35, /* adds r5, #8 */ + /* no_wrap: */ + 0x55, 0x60, /* str r5, [r2, #4] */ + 0x01, 0x39, /* subs r1, r1, #1 */ + 0x00, 0x29, /* cmp r1, #0 */ + 0x02, 0xd0, /* beq exit */ + 0xe3, 0xe7, /* b wait_fifo */ /* error: */ - 0x00, 0x20, /* movs r0, #0 */ - 0xc2, 0xf8, 0x02, 0x00, /* str r0, [r2, #2] */ + 0x00, 0x20, /* movs r0, #0 */ + 0x50, 0x60, /* str r0, [r2, #4] */ /* exit: */ - 0x30, 0x46, /* mov r0, r6 */ - 0x00, 0xbe, /* bkpt #0 */ + 0x30, 0x46, /* mov r0, r6 */ + 0x00, 0xbe, /* bkpt #0 */ }; /* flash write code */ |