diff options
| author | Spencer Oliver <spen@spen-soft.co.uk> | 2014-01-24 12:43:41 +0000 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2014-02-04 20:53:49 +0000 |
| commit | 47d4224d48199e700f7f685c7965a9864dde5f20 (patch) | |
| tree | 6b98262a327a53a4d77b740f726ac3f47bd86462 /doc | |
| parent | 698eaf9896b9b490676b13cf532c0161f7fb67c8 (diff) | |
doc: add missing reg command argument 'force'
The argument 'force' enables a user to bypass the internal cache and read
a target register directly. However it is missing from the user guide.
Change-Id: I26f689eec20b38a0dc5294626b25df566b554446
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1897
Tested-by: jenkins
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/openocd.texi | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index fd8767ed..f614c629 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -6372,7 +6372,7 @@ various operations. The current target may be changed by using @command{targets} command with the name of the target which should become current. -@deffn Command reg [(number|name) [value]] +@deffn Command reg [(number|name) [(value|'force')]] Access a single register by @var{number} or by its @var{name}. The target must generally be halted before access to CPU core registers is allowed. Depending on the hardware, some other @@ -6386,6 +6386,8 @@ which are also dirty (and will be written back later) are flagged as such. @emph{With number/name}: display that register's value. +Use @var{force} argument to read directly from the target, +bypassing any internal cache. @emph{With both number/name and value}: set register's value. Writes may be held in a writeback cache internal to OpenOCD, |