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author | Stefan Arnold <sarnold@sh-sw.de> | 2017-10-17 10:50:13 +0200 |
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committer | Tomas Vanek <vanekt@fbl.cz> | 2018-04-06 10:37:31 +0100 |
commit | be87994d60457ac846740dd9e5df3c8f63cf646e (patch) | |
tree | bcc70dff239f86d0e7832e61d49cacbe1a88a29c /doc/openocd.texi | |
parent | b08900badc3f51ac80b1b01de469e9fb7879f153 (diff) |
flash/nor/at91samd: Add "nvmuserrow" command.
Add option "nvmuserrow" to "at91samd" for changing and reading the register at 0x804000 which represents various fuses.
Change-Id: I6382cc4ac15e6b9681e2f30b0ae60397a6289c3b
Signed-off-by: Stefan Arnold <sarnold@sh-sw.de>
Reviewed-on: http://openocd.zylin.com/4260
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Diffstat (limited to 'doc/openocd.texi')
-rw-r--r-- | doc/openocd.texi | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index f6795e15..d0a3d49b 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -5319,6 +5319,26 @@ and prepares reset vector catch in case of reset halt. Command is used internally in event event reset-deassert-post. @end deffn +@deffn Command {at91samd nvmuserrow} +Writes or reads the entire 64 bit wide NVM user row register which is located at +0x804000. This register includes various fuses lock-bits and factory calibration +data. Reading the register is done by invoking this command without any +arguments. Writing is possible by giving 1 or 2 hex values. The first argument +is the register value to be written and the second one is an optional changemask. +Every bit which value in changemask is 0 will stay unchanged. The lock- and +reserved-bits are masked out and cannot be changed. + +@example +# Read user row +>at91samd nvmuserrow +NVMUSERROW: 0xFFFFFC5DD8E0C788 +# Write 0xFFFFFC5DD8E0C788 to user row +>at91samd nvmuserrow 0xFFFFFC5DD8E0C788 +# Write 0x12300 to user row but leave other bits and low byte unchanged +>at91samd nvmuserrow 0x12345 0xFFF00 +@end example +@end deffn + @end deffn @anchor{at91sam3} |