diff options
| author | David Brownell <dbrownell@users.sourceforge.net> | 2009-10-25 14:03:14 -0700 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-10-25 14:03:14 -0700 |
| commit | 19b84dafb0a9902df78aa021330cbcfae93a89a7 (patch) | |
| tree | e029e2405db792687990fbfc0b0a257404ce1c9b /TODO | |
| parent | e98817c4636f45b45db4332d2a5fbf36676f2f39 (diff) | |
ARM: rename "arm9tdmi vector_catch" to "arm9 ..."
And update doc accordingly. That EmbeddedICE register was
introduced for ARM9TDMI and then carried forward into most
new chips that use EmbeddedICE.
Diffstat (limited to 'TODO')
| -rw-r--r-- | TODO | 5 |
1 files changed, 2 insertions, 3 deletions
@@ -138,9 +138,8 @@ Once the above are completed: - regression: "reset halt" between 729(works) and 788(fails): @par https://lists.berlios.de/pipermail/openocd-development/2009-July/009206.html - ARM7/9: - - clean up "arm9tdmi vector_catch". Should be available for other arm9 - (e.g. arm926ejs) and some(???) arm7 cores. @par -https://lists.berlios.de/pipermail/openocd-development/2009-October/011488.html + - clean up "arm9tdmi vector_catch". Available for some arm7 cores? @par +https://lists.berlios.de/pipermail/openocd-development/2009-October/011488.html https://lists.berlios.de/pipermail/openocd-development/2009-October/011506.html - add reset option to allow programming embedded ice while srst is asserted. Some CPUs will gate the JTAG clock when srst is asserted and in this case, |