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authoroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2009-09-15 09:41:09 +0000
committeroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2009-09-15 09:41:09 +0000
commit379386743ac6bded1cefe8f8bfbaf2d6a5498493 (patch)
treeea6e77f0141547c8989c1e72836f970526b41465 /TODO
parent45674af63ad9ab9029abeff18237b9421dc0356a (diff)
added embedded ice programming while srst is asserted todo item
git-svn-id: svn://svn.berlios.de/openocd/trunk@2710 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'TODO')
-rw-r--r--TODO4
1 files changed, 4 insertions, 0 deletions
diff --git a/TODO b/TODO
index 7301e981..283ed5f3 100644
--- a/TODO
+++ b/TODO
@@ -114,6 +114,10 @@ Once the above are completed:
https://lists.berlios.de/pipermail/openocd-development/2009-July/009426.html
- regression: "reset halt" between 729(works) and 788(fails): @par
https://lists.berlios.de/pipermail/openocd-development/2009-July/009206.html
+- ARM7/9:
+ - add reset option to allow programming embedded ice while srst is asserted.
+ Some CPUs will gate the JTAG clock when srst is asserted and in this case,
+ it is necessary to program embedded ice and then assert srst afterwards.
- ARM923EJS:
- reset run/halt/step is not robust; needs testing to map out problems.
- ARM11 improvements (MB?)