tcl/target: make milandr configs swd-compatible

Change-Id: Ibb34f0d7829b205341bcce511ffc2624bdfe2c75
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1962
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>

2 files changed, 23 insertions, 14 deletions

diff --git a/tcl/target/1986ве1т.cfg b/tcl/target/1986ве1т.cfg
index 98d51031..0338297a 100644
--- a/tcl/target/1986ве1т.cfg
+++ b/tcl/target/1986ве1т.cfg
@@ -1,6 +1,8 @@
 # 1986ВЕ1Т
 # http://milandr.ru/index.php?mact=Products,cntnt01,details,0&cntnt01productid=236&cntnt01returnid=68
 
+source [find target/swj-dp.tcl]
+
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
 } else {
@@ -20,19 +22,14 @@ if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE 0x4000
 }
 
-# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
-
-adapter_nsrst_delay 100
-jtag_ntrst_delay 100
-
 #jtag scan chain
 if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
    set _CPUTAPID 0x4ba00477
+   # SWD IDCODE 0x2ba01477
 }
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
@@ -47,6 +44,14 @@ if { [info exists IMEMORY] && [string equal $IMEMORY true] } {
    flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 0 0 $_TARGETNAME 0 32 4
 }
 
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+adapter_khz 1000
+
+adapter_nsrst_delay 100
+if {$using_jtag} {
+   jtag_ntrst_delay 100
+}
+
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
 cortex_m reset_config sysresetreq
diff --git a/tcl/target/mdr32f9q2i.cfg b/tcl/target/mdr32f9q2i.cfg
index a37ed8f6..8e8262d7 100644
--- a/tcl/target/mdr32f9q2i.cfg
+++ b/tcl/target/mdr32f9q2i.cfg
@@ -1,6 +1,8 @@
 # MDR32F9Q2I (1986ВЕ92У)
 # http://milandr.ru/index.php?mact=Products,cntnt01,details,0&cntnt01productid=57&cntnt01returnid=68
 
+source [find target/swj-dp.tcl]
+
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
 } else {
@@ -20,19 +22,13 @@ if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE 0x8000
 }
 
-# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
-
-adapter_nsrst_delay 100
-jtag_ntrst_delay 100
-
 #jtag scan chain
 if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
    set _CPUTAPID 0x4ba00477
 }
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
@@ -46,6 +42,14 @@ if { [info exists IMEMORY] && [string equal $IMEMORY true] } {
    flash bank $_CHIPNAME.flash mdr 0x08000000 0x20000 0 0 $_TARGETNAME 0 32 4
 }
 
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+adapter_khz 1000
+
+adapter_nsrst_delay 100
+if {$using_jtag} {
+   jtag_ntrst_delay 100
+}
+
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
 cortex_m reset_config sysresetreq