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authorSalvador Arroyo <sarroyofdez@yahoo.es>2013-02-17 19:23:16 +0100
committerSpencer Oliver <spen@spen-soft.co.uk>2013-04-02 15:12:03 +0000
commitc185a5b72437594a79894dccd7ef8851b5789307 (patch)
tree1a9de7246e12f60de6cc090ab21e4c47c0584fa8
parent70fb53f90b4134cf10de3b504f56ec7c4a248b63 (diff)
pic32mx: false pending at low core clock
To show up the fail try to step with the core clock set to 31.25Khz and with a ftdi/hs adapter or with a wiggler, -not with ft2232-. The scan frequency should be set to 300Khz or higher, at lower frequency probably will not fail. The code exits with error because the pracc address is at 0x0. It also fails when using the "all" register, but in this case the code works without any message because the pracc address is at 0xff202004 when it fails. I never saw this fail with the core clock set to 500Khz or higher, but ... The workaround simply puts a 1 ms delay after the execution of the DERET instruction. Change-Id: I38e8c01a9c39aedd3282140543b83a0844d8ad29 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1139 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
-rw-r--r--src/target/mips_ejtag.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c
index 286fa327..a72731ef 100644
--- a/src/target/mips_ejtag.c
+++ b/src/target/mips_ejtag.c
@@ -245,7 +245,12 @@ int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info)
inst = MIPS32_DRET;
/* execute our dret instruction */
- return mips32_pracc_exec(ejtag_info, 1, &inst, 0, NULL, 0, NULL, 0);
+ int retval = mips32_pracc_exec(ejtag_info, 1, &inst, 0, NULL, 0, NULL, 0);
+
+ /* pic32mx workaround, false pending at low core clock */
+ jtag_add_sleep(1000);
+
+ return retval;
}
int mips_ejtag_init(struct mips_ejtag *ejtag_info)