diff options
| author | Erik Ahlén <erik.ahlen@avalonenterprise.com> | 2011-12-14 13:05:06 +0100 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2011-12-23 09:43:39 +0000 |
| commit | c402c1166bc314761c01d7f8afb700a2b14fceb6 (patch) | |
| tree | c2db6e20ad582ced8d0377f1233a68363fe5bdc1 | |
| parent | 8901fca0270fec41b12c30c7dbd806d460548c5b (diff) | |
Documentation for mxc NAND flash controller
Change-Id: I9e552491e8b4737c01e4f8ae2b9a582b6ff2bc5d
Signed-off-by: Erik Ahlén <erik.ahlen@avalonenterprise.com>
Reviewed-on: http://openocd.zylin.com/273
Tested-by: jenkins
Reviewed-by: Mathias Küster <kesmtp@freenet.de>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
| -rw-r--r-- | doc/openocd.texi | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index 37898591..68417bd7 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -5474,6 +5474,27 @@ in the MLC controller mode, but won't change SLC behavior. @end deffn @comment current lpc3180 code won't issue 5-byte address cycles +@deffn {NAND Driver} mx3 +This driver handles the NAND controller in i.MX31. The mxc driver +should work for this chip aswell. +@end deffn + +@deffn {NAND Driver} mxc +This driver handles the NAND controller found in Freescale i.MX +chips. It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35). +The driver takes 3 extra arguments, chip (@option{mx27}, +@option{mx31}, @option{mx35}), ecc (@option{noecc}, @option{hwecc}) +and optionally if bad block information should be swapped between +main area and spare area (@option{biswap}), defaults to off. +@example +nand device mx35.nand mxc imx35.cpu mx35 hwecc biswap +@end example +@deffn Command {mxc biswap} bank_num [enable|disable] +Turns on/off bad block information swaping from main area, +without parameter query status. +@end deffn +@end deffn + @deffn {NAND Driver} orion These controllers require an extra @command{nand device} parameter: the address of the controller. |