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authorMatthias Welwarsky <matthias.welwarsky@sysgo.com>2016-08-05 21:50:33 +0200
committerFreddie Chopin <freddie.chopin@gmail.com>2016-11-04 21:25:11 +0000
commit009943010420e49c2632769e9e21502b8166ba41 (patch)
tree254ff7ecdbcb9545b47e5f0093db75a280dc0000
parent75c3f4a25c9a1250ecba2eb40dbe1c4f16087184 (diff)
cortex_a/r/m: fix handling of un-examined cores
On multi-core systems, with some cores in power-down state, examination will fail for these cores. Make sure assert- and deassert_reset functions don't crash due to uninitialized variables. Change-Id: I472f8d19af2cd3c770c05f3e57a31b35a863b687 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3552 Tested-by: jenkins Reviewed-by: Jiri Kastner <cz172638@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
-rw-r--r--src/target/cortex_a.c26
-rw-r--r--src/target/cortex_m.c15
2 files changed, 31 insertions, 10 deletions
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 0a689eaf..256edbca 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -853,7 +853,8 @@ static int cortex_a_halt_smp(struct target *target)
head = target->head;
while (head != (struct target_list *)NULL) {
curr = head->target;
- if ((curr != target) && (curr->state != TARGET_HALTED))
+ if ((curr != target) && (curr->state != TARGET_HALTED)
+ && target_was_examined(curr))
retval += cortex_a_halt(curr);
head = head->next;
}
@@ -1156,7 +1157,8 @@ static int cortex_a_restore_smp(struct target *target, int handle_breakpoints)
head = target->head;
while (head != (struct target_list *)NULL) {
curr = head->target;
- if ((curr != target) && (curr->state != TARGET_RUNNING)) {
+ if ((curr != target) && (curr->state != TARGET_RUNNING)
+ && target_was_examined(curr)) {
/* resume current address , not in step mode */
retval += cortex_a_internal_restore(curr, 1, &address,
handle_breakpoints, 0);
@@ -1936,7 +1938,8 @@ static int cortex_a_assert_reset(struct target *target)
}
/* registers are now invalid */
- register_cache_invalidate(armv7a->arm.core_cache);
+ if (target_was_examined(target))
+ register_cache_invalidate(armv7a->arm.core_cache);
target->state = TARGET_RESET;
@@ -1952,17 +1955,22 @@ static int cortex_a_deassert_reset(struct target *target)
/* be certain SRST is off */
jtag_add_reset(0, 0);
- retval = cortex_a_poll(target);
- if (retval != ERROR_OK)
- return retval;
+ if (target_was_examined(target)) {
+ retval = cortex_a_poll(target);
+ if (retval != ERROR_OK)
+ return retval;
+ }
if (target->reset_halt) {
if (target->state != TARGET_HALTED) {
LOG_WARNING("%s: ran after reset and before halt ...",
target_name(target));
- retval = target_halt(target);
- if (retval != ERROR_OK)
- return retval;
+ if (target_was_examined(target)) {
+ retval = target_halt(target);
+ if (retval != ERROR_OK)
+ return retval;
+ } else
+ target->state = TARGET_UNKNOWN;
}
}
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 4566e2e7..4270f8f3 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -981,6 +981,18 @@ static int cortex_m_assert_reset(struct target *target)
bool srst_asserted = false;
+ if (!target_was_examined(target)) {
+ if (jtag_reset_config & RESET_HAS_SRST) {
+ adapter_assert_reset();
+ if (target->reset_halt)
+ LOG_ERROR("Target not examined, will not halt after reset!");
+ return ERROR_OK;
+ } else {
+ LOG_ERROR("Target not examined, reset NOT asserted!");
+ return ERROR_FAIL;
+ }
+ }
+
if ((jtag_reset_config & RESET_HAS_SRST) &&
(jtag_reset_config & RESET_SRST_NO_GATING)) {
adapter_assert_reset();
@@ -1101,7 +1113,8 @@ static int cortex_m_deassert_reset(struct target *target)
enum reset_types jtag_reset_config = jtag_get_reset_config();
if ((jtag_reset_config & RESET_HAS_SRST) &&
- !(jtag_reset_config & RESET_SRST_NO_GATING)) {
+ !(jtag_reset_config & RESET_SRST_NO_GATING) &&
+ target_was_examined(target)) {
int retval = dap_dp_init(armv7m->debug_ap->dap);
if (retval != ERROR_OK) {
LOG_ERROR("DP initialisation failed");