stm32f1x: fix bug in flash loader and restrict instruction set to armv6-m

Correct the offset to the read pointer when clearing it on error.

Also restrict the instruction set to armv6-m so the flash driver can be
used on Cortex-M0 parts with the same flash controller.

Change-Id: I380f9dabcc41fb6e4d43a7e02f355e2381913f39
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/399
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-by: Jonathan Dumaresq <jdumaresq@cimeq.qc.ca>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>

2 files changed, 51 insertions, 36 deletions

diff --git a/contrib/loaders/flash/stm32f1x.S b/contrib/loaders/flash/stm32f1x.S
index 125c76a6..e83d8c13 100644
--- a/contrib/loaders/flash/stm32f1x.S
+++ b/contrib/loaders/flash/stm32f1x.S
@@ -20,7 +20,7 @@
 
 	.text
 	.syntax unified
-	.cpu cortex-m3
+	.cpu cortex-m0
 	.thumb
 	.thumb_func
 	.global write
@@ -34,6 +34,7 @@
 	 * Clobbered:
 	 * r5 - rp
 	 * r6 - wp, tmp
+	 * r7 - tmp
 	 */
 
 #define STM32_FLASH_CR_OFFSET 0x10 /* offset of CR register from flash reg base */
@@ -48,24 +49,31 @@ wait_fifo:
 	beq 	wait_fifo
 	movs	r6, #1			/* set PG flag to enable flash programming */
 	str 	r6, [r0, #STM32_FLASH_CR_OFFSET]
-	ldrh	r6, [r5], #2	/* "*target_address++ = *rp++" */
-	strh	r6, [r4], #2
+	ldrh	r6, [r5]	/* "*target_address++ = *rp++" */
+	strh	r6, [r4]
+	adds	r5, #2
+	adds	r4, #2
 busy:
 	ldr 	r6, [r0, #STM32_FLASH_SR_OFFSET]	/* wait until BSY flag is reset */
-	tst 	r6, #1
+	movs	r7, #1
+	tst 	r6, r7
 	bne 	busy
-	tst 	r6, #0x14		/* check the error bits */
+	movs	r7, #0x14		/* check the error bits */
+	tst 	r6, r7
 	bne 	error
 	cmp 	r5, r3			/* wrap rp at end of buffer */
-	it  	cs
-	addcs	r5, r2, #8
+	bcc	no_wrap
+	mov	r5, r2
+	adds	r5, #8
+no_wrap:
 	str 	r5, [r2, #4]	/* store rp */
 	subs	r1, r1, #1		/* decrement halfword count */
-	cbz 	r1, exit		/* loop if not done */
-	b		wait_fifo
+	cmp     r1, #0
+	beq     exit		/* loop if not done */
+	b	wait_fifo
 error:
 	movs	r0, #0
-	str 	r0, [r2, #2]	/* set rp = 0 on error */
+	str 	r0, [r2, #4]	/* set rp = 0 on error */
 exit:
 	mov		r0, r6			/* return status in r0 */
 	bkpt	#0
diff --git a/src/flash/nor/stm32f1x.c b/src/flash/nor/stm32f1x.c
index b4ec93f6..02ab8c99 100644
--- a/src/flash/nor/stm32f1x.c
+++ b/src/flash/nor/stm32f1x.c
@@ -635,35 +635,42 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
 		/* #define STM32_FLASH_CR_OFFSET 0x10 */
 		/* #define STM32_FLASH_SR_OFFSET 0x0C */
 		/* wait_fifo: */
-			0x16, 0x68,             /* ldr  	r6, [r2, #0] */
-			0x00, 0x2e,             /* cmp  	r6, #0 */
-			0x1a, 0xd0,             /* beq  	exit */
-			0x55, 0x68,             /* ldr  	r5, [r2, #4] */
-			0xb5, 0x42,             /* cmp  	r5, r6 */
-			0xf9, 0xd0,             /* beq  	wait_fifo */
-			0x01, 0x26,             /* movs 	r6, #1 */
-			0x06, 0x61,             /* str  	r6, [r0, #STM32_FLASH_CR_OFFSET] */
-			0x35, 0xf8, 0x02, 0x6b, /* ldrh 	r6, [r5], #2 */
-			0x24, 0xf8, 0x02, 0x6b, /* strh 	r6, [r4], #2 */
+			0x16, 0x68,   /* ldr   r6, [r2, #0] */
+			0x00, 0x2e,   /* cmp   r6, #0 */
+			0x1a, 0xd0,   /* beq   exit */
+			0x55, 0x68,   /* ldr   r5, [r2, #4] */
+			0xb5, 0x42,   /* cmp   r5, r6 */
+			0xf9, 0xd0,   /* beq   wait_fifo */
+			0x01, 0x26,   /* movs  r6, #1 */
+			0x06, 0x61,   /* str   r6, [r0, #STM32_FLASH_CR_OFFSET] */
+			0x2e, 0x88,   /* ldrh  r6, [r5, #0] */
+			0x26, 0x80,   /* strh  r6, [r4, #0] */
+			0x02, 0x35,   /* adds  r5, #2 */
+			0x02, 0x34,   /* adds  r4, #2 */
 		/* busy: */
-			0xc6, 0x68,             /* ldr  	r6, [r0, #STM32_FLASH_SR_OFFSET] */
-			0x16, 0xf0, 0x01, 0x0f, /* tst  	r6, #1 */
-			0xfb, 0xd1,             /* bne  	busy */
-			0x16, 0xf0, 0x14, 0x0f, /* tst  	r6, #0x14 */
-			0x07, 0xd1,             /* bne  	error */
-			0x9d, 0x42,             /* cmp  	r5, r3 */
-			0x28, 0xbf,             /* it   	cs */
-			0x02, 0xf1, 0x08, 0x05, /* addcs	r5, r2, #8 */
-			0x55, 0x60,             /* str  	r5, [r2, #4] */
-			0x01, 0x39,             /* subs 	r1, r1, #1 */
-			0x19, 0xb1,             /* cbz  	r1, exit */
-			0xe4, 0xe7,             /* b    	wait_fifo */
+			0xc6, 0x68,   /* ldr   r6, [r0, #STM32_FLASH_SR_OFFSET] */
+			0x01, 0x27,   /* movs  r7, #1 */
+			0x3e, 0x42,   /* tst   r6, r7 */
+			0xfb, 0xd1,   /* bne   busy */
+			0x14, 0x27,   /* movs  r7, #0x14 */
+			0x3e, 0x42,   /* tst   r6, r7 */
+			0x08, 0xd1,   /* bne   error */
+			0x9d, 0x42,   /* cmp   r5, r3 */
+			0x01, 0xd3,   /* bcc   no_wrap */
+			0x15, 0x46,   /* mov   r5, r2 */
+			0x08, 0x35,   /* adds  r5, #8 */
+		/* no_wrap: */
+			0x55, 0x60,   /* str   r5, [r2, #4] */
+			0x01, 0x39,   /* subs  r1, r1, #1 */
+			0x00, 0x29,   /* cmp   r1, #0 */
+			0x02, 0xd0,   /* beq   exit */
+			0xe3, 0xe7,   /* b     wait_fifo */
 		/* error: */
-			0x00, 0x20,             /* movs 	r0, #0 */
-			0xc2, 0xf8,	0x02, 0x00, /* str  	r0, [r2, #2] */
+			0x00, 0x20,   /* movs  r0, #0 */
+			0x50, 0x60,   /* str   r0, [r2, #4] */
 		/* exit: */
-			0x30, 0x46,             /* mov  	r0, r6 */
-			0x00, 0xbe,             /* bkpt 	#0 */
+			0x30, 0x46,   /* mov   r0, r6 */
+			0x00, 0xbe,   /* bkpt  #0 */
 	};
 
 	/* flash write code */