diff options
author | Spencer Oliver <spen@spen-soft.co.uk> | 2012-07-04 21:19:17 +0100 |
---|---|---|
committer | Andreas Fritiofson <andreas.fritiofson@gmail.com> | 2012-07-11 10:32:39 +0000 |
commit | 1df6e59178d1ce7d466a1c9821a1ea88b8df3e4a (patch) | |
tree | 00f90b0c8755a62ad35fa73fb391c6d67e415b39 | |
parent | 07251ab8d81b2b5491af673b694bebbbc574c112 (diff) |
flash: add stm32f3x support
add support for the new stm32f3x family from stmicro:
http://www.st.com/stm32f3
Change-Id: Icd1db95bb2767d9c0ecef24deefa92b4fdaa4f14
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/735
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
-rw-r--r-- | src/flash/nor/stm32f1x.c | 56 | ||||
-rw-r--r-- | tcl/target/stm32f3x.cfg | 63 | ||||
-rw-r--r-- | tcl/target/stm32f3x_stlink.cfg | 20 |
3 files changed, 139 insertions, 0 deletions
diff --git a/src/flash/nor/stm32f1x.c b/src/flash/nor/stm32f1x.c index f05a4aaa..e7e795d3 100644 --- a/src/flash/nor/stm32f1x.c +++ b/src/flash/nor/stm32f1x.c @@ -830,6 +830,9 @@ static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id) } else if (((cpuid >> 4) & 0xFFF) == 0xC23) { /* 0xC23 is M3 devices */ device_id_register = 0xE0042000; + } else if (((cpuid >> 4) & 0xFFF) == 0xC24) { + /* 0xC24 is M4 devices */ + device_id_register = 0xE0042000; } else { LOG_ERROR("Cannot identify target as a stm32x"); return ERROR_FAIL; @@ -858,6 +861,9 @@ static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_i } else if (((cpuid >> 4) & 0xFFF) == 0xC23) { /* 0xC23 is M3 devices */ flash_size_reg = 0x1FFFF7E0; + } else if (((cpuid >> 4) & 0xFFF) == 0xC24) { + /* 0xC24 is M4 devices */ + flash_size_reg = 0x1FFFF7CC; } else { LOG_ERROR("Cannot identify target as a stm32x"); return ERROR_FAIL; @@ -957,6 +963,17 @@ static int stm32x_probe(struct flash_bank *bank) LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash"); flash_size_in_kb = 128; } + } else if ((device_id & 0xfff) == 0x422) { + /* stm32f30x - we have 2k pages + * 2 pages for a protection area */ + page_size = 2048; + stm32x_info->ppage_size = 2; + + /* check for early silicon */ + if (flash_size_in_kb == 0xffff) { + LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash"); + flash_size_in_kb = 256; + } } else if ((device_id & 0xfff) == 0x428) { /* value line High density - we have 2k pages * 4 pages for a protection area */ @@ -993,6 +1010,17 @@ static int stm32x_probe(struct flash_bank *bank) stm32x_info->register_base = FLASH_REG_BASE_B1; base_address = 0x08080000; } + } else if ((device_id & 0xfff) == 0x432) { + /* stm32f37x - we have 2k pages + * 2 pages for a protection area */ + page_size = 2048; + stm32x_info->ppage_size = 2; + + /* check for early silicon */ + if (flash_size_in_kb == 0xffff) { + LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash"); + flash_size_in_kb = 256; + } } else if ((device_id & 0xfff) == 0x440) { /* stm32f0x - we have 1k pages * 4 pages for a protection area */ @@ -1162,6 +1190,20 @@ static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size) snprintf(buf, buf_size, "unknown"); break; } + } else if ((device_id & 0xfff) == 0x422) { + printed = snprintf(buf, buf_size, "stm32f30x - Rev: "); + buf += printed; + buf_size -= printed; + + switch (device_id >> 16) { + case 0x1000: + snprintf(buf, buf_size, "1.0"); + break; + + default: + snprintf(buf, buf_size, "unknown"); + break; + } } else if ((device_id & 0xfff) == 0x428) { printed = snprintf(buf, buf_size, "stm32x (Value HD) - Rev: "); buf += printed; @@ -1194,6 +1236,20 @@ static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size) snprintf(buf, buf_size, "unknown"); break; } + } else if ((device_id & 0xfff) == 0x432) { + printed = snprintf(buf, buf_size, "stm32f37x - Rev: "); + buf += printed; + buf_size -= printed; + + switch (device_id >> 16) { + case 0x1000: + snprintf(buf, buf_size, "1.0"); + break; + + default: + snprintf(buf, buf_size, "unknown"); + break; + } } else if ((device_id & 0xfff) == 0x440) { printed = snprintf(buf, buf_size, "stm32f0x - Rev: "); buf += printed; diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg new file mode 100644 index 00000000..1f051434 --- /dev/null +++ b/tcl/target/stm32f3x.cfg @@ -0,0 +1,63 @@ +# script for stm32f3x family + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32f3x +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# Work-area is a space in RAM used for flash programming +# By default use 16kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x4000 +} + +# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz +# +# Since we may be running of an RC oscilator, we crank down the speed a +# bit more to be on the safe side. Perhaps superstition, but if are +# running off a crystal, we can run closer to the limit. Note +# that there can be a pretty wide band where things are more or less stable. +adapter_khz 1000 + +adapter_nsrst_delay 100 +jtag_ntrst_delay 100 + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + # See STM Document RM0316 + # Section 29.6.3 - corresponds to Cortex-M4 r0p1 + set _CPUTAPID 0x4ba00477 +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +if { [info exists BSTAPID] } { + set _BSTAPID $BSTAPID +} else { + # See STM Document RM0316 + # Section 29.6.2 + set _BSTAPID 0x06432041 +} +jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME + +# if srst is not fitted use SYSRESETREQ to +# perform a soft reset +cortex_m3 reset_config sysresetreq diff --git a/tcl/target/stm32f3x_stlink.cfg b/tcl/target/stm32f3x_stlink.cfg new file mode 100644 index 00000000..bc86ed94 --- /dev/null +++ b/tcl/target/stm32f3x_stlink.cfg @@ -0,0 +1,20 @@ +# +# STM32f3x stlink pseudo target +# + +if { [info exists CHIPNAME] == 0 } { + set CHIPNAME stm32f3x +} + +if { [info exists CPUTAPID] == 0 } { + set CPUTAPID 0x1ba01477 +} + +if { [info exists WORKAREASIZE] == 0 } { + set WORKAREASIZE 0x4000 +} + +source [find target/stm32_stlink.cfg] + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME |