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authorAntonio Borneo <borneo.antonio@gmail.com>2019-06-24 12:17:17 +0200
committerAntonio Borneo <borneo.antonio@gmail.com>2020-03-12 10:05:30 +0000
commitf447c31b30f805725b7a09d51d786c88de4b7a4f (patch)
tree5aeda229b2c24f84856b7843fa1e89d65ad7df37
parentfbbfbb2516a58b2ab866d713ef18c0a210bb647b (diff)
arm: fix reg num for Monitor mode
Commit 2efb1f14f611 ("Add GDB remote target description support for ARM4") inserts two additional registers "sp" and "lr" in the table arm_core_regs[], thus shifting by two the position of the last three registers already present "sp_mon" moved from index 37 to 39 "lr_mon" moved from index 38 to 40 "spsr_mon" moved from index 39 to 41 Part of the code is updated (e.g. enum defining ARM_SPSR_MON and array arm_mon_indices[]), but it's missing the update of mapping in armv4_5_core_reg_map[]. Fix armv4_5_core_reg_map[]. Change-Id: I0bdf766183392eb738206b876cd9559aacc29fa0 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Fixes: 2efb1f14f611 ("Add GDB remote target description support for ARM4") Reviewed-on: http://openocd.zylin.com/5257 Tested-by: jenkins
-rw-r--r--src/target/armv4_5.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 6c487626..6d038571 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -414,7 +414,7 @@ const int armv4_5_core_reg_map[8][17] = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
},
{ /* MON */
- 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 37, 38, 15, 39,
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 39, 40, 15, 41,
}
};