diff options
| author | Matthias Welwarsky <matthias.welwarsky@sysgo.com> | 2019-04-11 10:22:27 +0200 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2020-03-12 09:48:25 +0000 |
| commit | afe899f938a8edb3657c9455fc5caefcaef7e65f (patch) | |
| tree | f222290e7537ea0ccb42515c7b9ecfead38b83fb | |
| parent | a8b1bd8376ad30e8ffe7d4d87ed0b041d7adbe76 (diff) | |
cortex_a: warn on broken debug_base setting
A common problem with target configurations appears to be broken
debug base address configuration. ARM DDI0406C.d specifies in App. D,
1.4.1, that bit 31 of the debug base address serves as identification
of an external debugger, as opposed to an internal access to memory
mapped debug registers by the CPU. External accesses are treated
as privileged and require no debug authentification via the lock
access register.
Sometimes the base address of a debug component is wrong even
in the targets' ROM table. In this case, the correct base address
must be specified using the -dbgbase argument when creating the
target.
This patch adds a warning when bit 31 of the debug base address
is not set, as a hint to the user.
Change-Id: I9c41d85a138123c657ef655e3436a2aa39249dcc
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/5105
Tested-by: jenkins
Reviewed-by: Tommy Vestermark <tov@vestermark.dk>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
| -rw-r--r-- | src/target/cortex_a.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 8773ea16..a79b0b90 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -2718,6 +2718,10 @@ static int cortex_a_examine_first(struct target *target) } else armv7a->debug_base = target->dbgbase; + if ((armv7a->debug_base & (1UL<<31)) == 0) + LOG_WARNING("Debug base address for target %s has bit 31 set to 0. Access to debug registers will likely fail!\n" + "Please fix the target configuration.", target_name(target)); + retval = mem_ap_read_atomic_u32(armv7a->debug_ap, armv7a->debug_base + CPUDBG_DIDR, &didr); if (retval != ERROR_OK) { |